Handling contiguous memory references in a multi-queue system

DETAILED DESCRIPTION What is claimed is: 1.
A controller for a random access memory comprises: control logic, including an arbiter that detects a status of outstanding memory references to select a memory reference from one of a plurality of queues of memory references, said control logic responsive to a memory reference chaining bit that when set allows for special handling of contiguous memory references, the special handling allows the arbiter to service a same queue until the memory reference chaining bit is cleared.
2.
The controller of claim 1 wherein consecutive memory references from a thread that has the memory reference chaining bit set, are used to form continuous byte aligned read blocks from discontinuous memory buffers.
3.
The controller of claim 1 wherein consecutive memory references from a thread that has the memory reference chaining bit set, are used to optimize performance when consecutive data writes are to the same SDRAM page.
4.
The controller of claim 1 wherein assertion of the memory reference chaining bit causes the arbiter to select a functional unit that previously requested access to a memory system.
5.
The controller of claim 1, further comprising: an address and command queue that holds memory references from a plurality of micro control functional units; a first read/write queue that holds memory reference from a computer bus; a second read/write queue that holds memory references from a core processor; and wherein the address and command queue comprises: a high priority queue that holds memory references from high priority tasks.
6.
The controller of claim 5, wherein the control logic is responsive to an optimized memory bit and the memory reference chaining bit, and wherein assertion of the memory reference chaining bit causes the arbiter to maintain the memory references from a current queue.
7.
The controller of claim 5 wherein when the memory reference chaining bit is set, the arbiter continues to service memory requests from the same queue until the memory reference chaining bit is cleared