Load and store unit for a vector processor

DETAILED DESCRIPTION A load/store unit within a vector processor services memory requests to load or store vectors (multiple data elements of a substantially similar type).
Such an apparatus provides the advantage of handling vectors instead of individual data elements.
Further, such an apparatus provides the advantage of performing parallel calculations using multimedia data structures, thereby increasing the performance of processors required to perform such calculations.
In one embodiment of the invention, an apparatus is coupled to a requesting unit and a memory.
The apparatus includes a data path and a request control circuit.
The data path is coupled to the requesting unit and the memory.
The data path is for buffering a vector.
The vector includes multiple data elements of a substantially similar data type.
The request control circuit is coupled to the data path and the requesting unit and receives a vector memory request from the requesting unit.
The request control circuit services the vector memory request by causing the transference of the vector between the requesting unit and the memory via the data path.
In a further embodiment, the apparatus is a load/store unit for a vector processor.
In yet a further embodiment, the apparatus is a vector load unit.
In still yet a further embodiment, the apparatus is a vector store unit.
In another embodiment of the invention, a computer system includes a vector processor, a memory and a load store unit.
The load/store unit is coupled to the vector processor and the memory and includes a read/write data path and a request control circuit.
The read/write data path is for buffering vectors.
Each of the vectors includes multiple data elements of a substantially similar data type.
The request control circuit is coupled to the read/write data path and the vector processor.
The request control circuit is for receiving vector memory requests from the vector processor.
The request control circuit services the vector memory requests by causing the transference of the vectors corresponding to the vector memory requests between the vector processor and the memory via the read/write data path