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Low power, high speed communications bus
| Details |
Inventors: Sherman, David L.;
Assignee: Gigabus, Inc. (Fremont, CA)
Primary Examiner: Follansbee; John A.
Assistant Examiner:
Attorney, Agent or Firm: Gray, Cary Ware & Freidenrich
A low power, high speed communications bus is provided which may interconnect semiconductor dies or computer modules over short distances. The bus may be operated in either a mesosynchronous mode of operation or asynchronous mode of operation so that the bus does not require a phase locked loop (PLL). In addition, the bus does not require termination due to the programmed `series termination` in combination with strict limits on the time of flight on the bus versus the slew rate of the signals. The bus may also permit the port sizes connected to the bus to be reconfigured on the fly to provide "quality of service support for buses". The bus may also provide multiple independent data streams that may be controlled by a single address/command bus. The bus may also provide a pair of wires which carry two signals (e.g., a TStrb/Ren signal on one wire and a RStrb/Ten signal on the other wire) between each port to communicate the strobe signals between the ports. |
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DETAILED DESCRIPTION The solution to the problem of data communication between a CPU and a memory where the internal speed of the CPU is mismatched to the access speed of the memory is a high speed bus in accordance with the invention which is specifically designed to take advantage of various advanced packaging techniques.
Although none of the conventional buses provide a solution for communicating over very short distances, the invention provides a bus tailored to work over the very short distances associated with multi-chip modules and which provides chip scale point-to-point connections.
Due to the short distances of the data communications (e.
g.
, about 1-5 cm), the high speed bus in accordance with the invention may have a high speed and a wide bandwidth to solve the current mismatch between the speed of the CPU and the access speed to the memory.
The invention provides a bus architecture for highly local interconnects by using a very efficient signaling convention that has the lowest energy expended per bit transmitted, the highest possible bandwidth and the lowest possible latency compared to existing high speed interconnect architectures.
The invention solves the data access speed problems of the fastest processors and graphics engines for the foreseeable future.
The bus, however, may also be applied to cost sensitive, high volume consumer products that require a small form factor and long battery life without sacrificing performance because the bus uses less power and consequently will extend the battery life and generate less heat than the conventional solutions.
The invention also provides a low power, short signaling distance communications bus which may be used to communicate data between, for example, semiconductor dies attached to a printed circuit board.
The bus may provide asynchronous or mesochronous bus communications which reduces the overall power necessary for the bus since the clock signal is not transferred around the bus.
In addition, the asynchronous communications protocol permits the latency of the bus to decrease because the speed of the retrieval of data is not limited by the clock speed and the timeslots assigned in a conventional bus
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