Memory controller with priority queues

DETAILED DESCRIPTION In an illustrative embodiment of the invention, a memory controller receives reads, memory writes, and cache writes.
A pending read is selected and issued to memory.
When a response is received from memory, all cache writes are checked to determine whether any correspond to the pending read.
If there is a corresponding cache write, the data from the corresponding cache write is used to respond to the pending read.
If there is not a corresponding cache write, then prior memory writes are checked to determine whether any correspond to the pending read.
If there is a corresponding prior memory write, the data from the corresponding prior memory write is used to respond to the pending read.
A coherency check from associated caches may also be performed, and the appropriate data returned to the processor that requested the read.
In another illustrative embodiment of the invention, a memory controller includes three queues to control the order in which memory access is performed.
A read queue that contains read requests is typically given highest priority, and therefore reads are generally serviced first.
A wait queue contains read requests and memory write requests, and is incremented to the pending read before the pending read is completed.
As the wait queue is incremented, memory writes from the wait queue are entered onto a ready queue.
Each request retrieved from the wait queue is checked against pending requests in the ready queue.
Cache writes are entered directly onto the ready queue.
When either a conflict is detected for the pending ready, or when the ready queue contains a certain amount of requests, the ready queue is flushed.
Flushing the ready queue includes retrieving the next request from the ready queue, checking the next request against requests in the wait queue for conflicts, and performing the request.