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Method and apparatus for arbitrating between command streams
| Details |
Inventors: Harriman, David J.; Langendorf, Brian K.; Ajanovic, Jasmin;
Assignee: Intel Corporation (Santa Clara, CA)
Primary Examiner: Cabeca; John W.
Assistant Examiner: Bataille; Pierre-Michel
Attorney, Agent or Firm: Draeger; Jeffrey S.
A method and apparatus for arbitrating between command streams. The method unblocks high priority commands which are blocked and then selects any remaining high priority commands. Normal priority commands are selected after the high priority commands. A memory controller described includes a command queue block having a plurality of command queues, each being coupled to receive a different type of command. The memory controller also includes arbitration logic which, among other things, selects high priority read commands before high priority write commands. Memory interface logic generates memory accesses performing commands selected by the arbitration logic. |
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DETAILED DESCRIPTION The present invention provides a method and apparatus for arbitrating between command streams.
In the following description, numerous specific details such as command priorities and types, queue arrangements, and system configurations are set forth in order to provide a more thorough understanding of the present invention.
It will be appreciated, however, by one skilled in the art that the invention may be practiced without such specific details.
In other instances, control structures and gate level circuits have not been shown in detail in order not to obscure the invention.
Those of ordinary skill in the art, with the included functional descriptions, will be able to implement the necessary logic circuits without undue experimentation.
As will be further discussed below, the present invention provides an approach to arbitration between command streams for efficient memory access.
The techniques described achieve targeted command latencies by favoring high priority commands, especially blocked high priority commands.
Additionally, improving locality of reference by favoring same page reads may bolster efficiency, as may reducing turn around by preferring the same type of command as last selected.
FIG.
1 illustrates one embodiment of a command arbitration algorithm which may be executed by a memory controller 200 illustrated in FIG.
2.
The memory controller 200 provides a processor 205, a system bus 225, and a bus agent 215 access to a memory 210.
In one embodiment, the memory 210 is a dynamic random access memory system; however, in alternate embodiments, the memory 210 may be mechanical storage such as a hard drive or other input/output device, or may be an abstract memory space including disk space, static and/or dynamic memory, and other memory devices.
In one embodiment a system arbiter 245 handles a first type of command from the bus agent 215, the system bus 225, and the processor 205, while a scheduler 230 handles a second type of command from the bus agent 215
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