Method and apparatus for locally generating addressing information for a memory access

DETAILED DESCRIPTION The present invention overcomes many of the disadvantages of the prior art by providing a system whereby a processor or the like need not provide an address to a memory unit for each read and/or write operation when successive address locations are accessed.
That is, for multiple memory accesses which access successive address locations, the processor or the like may provide an initial address but thereafter may not be required to provide subsequent addresses to the memory unit.
The subsequent addresses may be automatically generated by an automatic-increment block.
This may have a number of advantages.
For example, a processor or the like may provide an initial address to the memory unit and then may be free to perform other tasks while the number of successive read and/or write operations are made to a memory unit.
That is, the processor or the like may perform a "block" read and/or write operation of the memory unit wherein a predefined number of successive address locations may be read and/or written without the support of the processor or the like.
The processor may specify the predefined number of successive addresses to access in advance.
For a number of successive read operations, the processor may only need to read the data provided by the memory unit.
For a number of successive write operations, the processor may only need to provide the write data to the memory unit.
To ensure the processor of the like is free to process other tasks during a "block" read and/or write operation, a buffer block may be provided in the processor wherein the buffer block may write or read the necessary data to/from the memory unit.
Another advantage of the present invention is that many of the disadvantages of the modified common bus approach discussed above may be overcome while maintaining the advantages thereof.
As stated above, the modified common bus approach may reduce the number of signal traces that must be provided on a corresponding PC board.
Further, the modified common bus approach may limit the amount of power required to charge and discharge the corresponding bus traces