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Method and apparatus for packetizing data into a data stream
| Details |
Inventors: O'Loughlin, Gareth P.; Patoine, Michel J. P.; Smail, J. Morgan;
Assignee: Alcatel Canada Inc. (Kanata, CA)
Primary Examiner: Marcelo; Melvin
Assistant Examiner: Trinh; D.
Attorney, Agent or Firm:
A method and apparatus for packetizing data include processing that begins by determining the bit time occurrence for retrieval of at least one bit of a portion of a data word, which is stored in local memory. Next, the processing determines the status of the data word based on the bit time occurrence for retrieval of the bit. Next, the bit is retrieved from local memory based on the status of the data word. Having retrieved the bit, the status of the data word is updated based on the bit time occurrence of the at least one bit and the data word. Next, the processing applies a data packetizing protocol to the at least one retrieved bit based on the status of the data word to construct a data packet corresponding to the data word. |
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DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT Generally, the present invention provides a method and apparatus for packetizing data.
Such processing begins by determining the bit time occurrence for retrieval of at least one bit of a portion of a data word, which is stored in local memory.
Next, the processing determines the status of the data word based on the bit time occurrence for retrieval of the bit.
Next, the bit is retrieved from local memory based on the status of the data word.
Having retrieved the bit, the status of the data word is updated based on the bit time occurrence of the at least one bit and the data word.
Next, the processing applies a data packetizing protocol to the at least one retrieved bit based on the status of the data word to construct a data packet corresponding to the data word.
With such a method and apparatus, data packetizing may be done at the bit level, or groups of bit level, thereby providing much greater flexibility in the retrieval and packetizing of data.
Further, when such a packetizing process incorporated into DS3 switching equipment, it is capable of supporting up to 672 logical channels or when incorporated into E3 switching equipment, it is capable of supporting 512 logical channels.
In general, the present invention teaches a system, and portions thereof, for the termination and generation of up to 672 HDLC encapsulated channels within DS3 switching equipment (i.
e.
, data transport system) or up to 496 channels in E3 switching equipment (i.
e.
, data transport system).
The data transport systems may be configured to provide interface adaptation to ATM or cross-connection to HDLC encapsulated networks.
The data transport system includes a plurality of transport mapping circuits that may be manufactured as printed circuits.
The transport mapping circuits may each include a single integrated circuit (IC) solution for multi-channel HDLC processing and buffer management to support the DS3/E3 rates.
The multi-channel HDLC IC includes a plurality of virtual HDLC modules that support ingress data packets and egress data packets
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