 Dynamic multiplexing of hyperlinks and bookmarks |
| The foregoing and other problems are overcome and the objects of the invention are realized by ... |
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| Electric motor including unitary brush card bushing holder |
| Referring now to FIGS. 2-7, there is depicted a motor 10 which is ideally suited for driving a fan ... |
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| Electric motor brush assembly |
| In accordance with one aspect of the present invention, an electric motor brush assembly is ... |
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| Methods and apparatus for managing multiple user systems |
| The techniques of the present invention relate to allocating resources and managing multiple ... |
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| Image search apparatus and method |
| The present invention has been made in consideration of the above problems, and has as its object ... |
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| Multi-tier debugging |
| To overcome the limitations in the prior art described above, and to overcome other limitations ... |
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| Multiple user software debugging system |
| Multiple User Computing Environment--FIG. 1 FIG. 1 illustrates a block diagram example of a ... |
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| Management of network distributed agents in a distributed computing environment |
| OF THE PREFERRED EMBODIMENT OF THE PRESENT INVENTION Reference now being made to FIG. 1, a ... |
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| Methods, systems and computer program products for remote control of a processing system |
| It is, therefore, one object of the present invention to provide a computer system that can control ... |
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| Processes and apparatuses for managing network devices |
| Accordingly, it is an object of the present invention to obviate the above-described problems and ... |
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Method and apparatus for refreshing a non-clocked memory
| Details |
Inventors: Bermingham, Michael; MacLellan, Christopher S.; Sheikh, Rizwan;
Assignee: EMC Corporation (MA)
Primary Examiner: Nguyen; Hiep T
Assistant Examiner:
Attorney, Agent or Firm: Michaelis, Esq.; Brian L., Miles, Esq.; Jacques B. Brown Rudnick Freed & Gesmer, PC
An optimized memory refresh scheme controls and reduces instantaneous power consumption and power-related noise during DRAM refresh. In the optimized refresh implementation the DRAM is refreshed using a selectable overlap Column Address Select (CAS) before Row Address Select (RAS) refresh mode. A refresh interface between a host port and the memory system is over two bussed signals comprised of a Refresh Enable signal (Refresh.sub.-- Enable) and a Refresh Strobe pulse train (Refresh.sub.-- Strobe). Refresh.sub.-- Enable is issued by the host port to define a refresh operation. Refresh.sub.-- Strobe is a pulse train generated by the host port which is used as a clock for a sequential refresh sequencer. A refresh sequencer issues selectably timed column address refresh and row address refresh signals according to which the memory banks can all be selectably refreshed substantially in parallel, or with a predetermined selected level of overlap. Optimized skewing can be implemented to minimize the time for refresh. Refreshing of different memory banks can be selectably overlapped to provide acceptable current and noise profiles during refresh. |
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DETAILED DESCRIPTION OF THE INVENTION A combinatorial decoding device and/or programmable refresh according to the invention is implemented in the context of a multiple port, multiple bank shared memory array system, such as illustrated in FIG.
2.
In this illustrative embodiment, a multi-port redundant architecture is implemented having two ports each controlled by respective port controllers 30, 32 (port controller A and port controller B), configured so that each port can access the shared memory as a fully independent channel.
The port controllers 30, 32, issue control and address signals to a plurality of shared memory banks.
The shared memory banks in this embodiment are comprised of four daughter boards 34, 36, 38, 40 each of which has 16M.
times.
4 Dynamic Random Access Memory (DRAM) chips organized as eight banks of memory with 128 Megabytes per bank.
Each of the four daughter boards 34, 36, 38, 40, includes a respective memory array decoder ASIC or device according to the invention 42, 44, 46, 48.
Each of the memory array decoder devices 42, 44, 46, 48 is connected to each of the port controllers 30, 32, via a control ASIC interface or bus 33 that provides address signals and control signals.
In this illustrative embodiment the control signals are comprised of three bits for bank select signals (BANK.
sub.
-- SEL), four bits for column address select (CAS), four bits for row address select (RAS), and four bits for write enable signals (WR).
The memory array decoder ASICs 42, 44, 46, 48 are block diagrammatically illustrated in FIG.
3.
Each device is comprised of parity logic 50 generating address parity as known in the art, an address buffer/decoder 52 according to the invention which receives address and control signals and issues address and control signals only to the selected memory bank, and a refresh state machine 54 which receives refresh enable and strobe signals and effects optimized refresh according to the invention as described in detail hereinafter.
The address buffer/decoder 52 according to the invention illustrated in greater detail in FIGS
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