 High-speed data bus for network switching |
| The specification will be organized as follows: 1. BlazePath.TM./BlazeFire.TM. Architecture/Chip S... |
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| Method and apparatus for data buffer management in a communications switch |
| OF A PREFERRED EMBODIMENT OF THE INVENTION Generally, the present invention provides a method and ... |
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| Handling contiguous memory references in a multi-queue system |
| What is claimed is: 1. A controller for a random access memory comprises: control logic, including ... |
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| Communication between processors |
| Referring to FIG. 1, a computer system 26 includes two processors 1, 2. Each processor 1, 2 has a ... |
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| Optimizations to receive packet status from fifo bus |
| According to one aspect of the invention, a method is described of receiving bytes of data from a ... |
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| Storing frame modification information in a bank in memory |
| The present invention comprises a method and system for reserving frame modification information ... |
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| Scratchpad memory |
| According to one aspect, a integrated circuit includes a random-access memory (RAM) storage and a ... |
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| Read lock miss control and queue management |
| According to one aspect of the invention, a method is described of managing memory access to random ... |
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Method and system for executing a program within a multiscalar processor by processing linked thread descriptors
| Details |
Inventors: Kahle, James A.; Mallick, Soummya; McDonald, Robert G.; Swarthout, Edward L.;
Assignee: International Business Machines Corporation (Armonk, NY)
Primary Examiner: Banankhah; Majid
Assistant Examiner:
Attorney, Agent or Firm: Salys; Casimer K. Felsman, Bradley, Vaden, Gunter & Dillon, LLP
A multiscalar processor and method of executing a multiscalar program within a multiscalar processor having a plurality of processing elements and a thread scheduler are provided. The multiscalar program includes a plurality of threads that are each composed of one or more instructions of a selected instruction set architecture. Each of the plurality of threads has a single entry point and a plurality of possible exit points. The multiscalar program further comprises thread code including a plurality of data structures that are each associated with a respective one of the plurality of threads. According to the method, a third data structure among the plurality of data structures is supplied to the thread scheduler. The third data structure, which is associated with a third thread among the plurality of threads, specifies a first data structure associated with a first possible exit point of the third thread and a second data structure associated with a second possible exit point of the third thread. The third thread is assigned to a selected one of the plurality of processing elements for execution. Prior to completing execution of the third thread, the thread scheduler selects from among the first and the second possible exit points of the third thread. In response to the selection, a corresponding one of the first and second data structures is loaded into the thread scheduler for processing. |
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DETAILED DESCRIPTION The multiscalar processing paradigm disclosed herein overcomes numerous deficiencies of the previously proposed multiscalar paradigm through improvements to both the multiscalar hardware and software architectures.
In order to facilitate an understanding of the operation of the multiscalar processor hardware, an introduction to the improved multiscalar software architecture will first be given.
Software Architecture With reference now to the figures and in particular with reference to FIG.
1A, there is a conceptual diagram of a process for constructing a multiscalar program is illustrated.
As depicted, an ordinary high level language (e.
g.
, C++) program 10 containing a number of high level instructions 12 is input into multiscalar compiler 14 for processing.
During a first pass, multiscalar compiler 14 translates each of high level instructions 12 into one or more executable instruction set architecture (ISA) instructions 16 arranged in a particular program order.
In addition, multiscalar compiler 14 partitions ISA instructions 16 into one or more threads 18, which each contain a logically contiguous group of ISA instructions 16.
As utilized hereinafter, the term thread refers to a set of one or more logically contiguous instructions within a multiscalar program that have a single entry point and multiple possible exit points.
In other words, when a thread is executed, the first instruction within the thread is always executed, but there are multiple possible execution paths out of the thread.
Importantly, the multiscalar software architecture disclosed herein permits each ISA instruction 16 to be included within more than one thread 18 and does not utilize the explicit programmed forks required by conventional multiple processor software architectures.
Threads 18 can be distinguished from basic blocks 20 in that basic blocks 20 are sets of sequential ISA instructions terminated by a branch instruction.
Basic blocks 20 have only two exit points, but may have two or more entry points
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