Method, system, and program for managing requests to a cache using flags to queue and dequeue data in a buffer

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description, reference is made to the accompanying drawings which form a part hereof and which illustrate several embodiments of the present invention.
It is understood that other embodiments may be utilized and structural and operational changes may be made without departing from the scope of the present invention.
Computing Environment FIG.
2 illustrates a computing environment with an arrangement of a cache and memory device including a circular buffer in which preferred embodiments are implemented.
The computing environment includes a queue user 52, which may comprise a processor unit, CPU, hardware, etc.
, and a cache 54.
The cache 54 would include a directory of the data stored in cache, data, and control logic to use the directory to access entries in cache.
A main memory 60 may be comprised of any volatile memory device known in the art, such as a Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Random Access Memory (RAM), etc.
The main memory 60 includes a circular buffer data structure 62 having head and tail pointers 64 and 66 in a manner known in the art.
As shown, the main memory 60 may include multiple circular buffers accessible to the queue user 52.
To access data from the main memory 60, the cache 54 must access the data via a bus 68 or memory read/write interface in a manner known in the art.
The cache 54 would store data blocks in the memory included in the circular buffer 62 to provide the queue user 52 faster access to the data in the circular buffer 62 than can be provided from the main memory 60.
Entries from the circular buffer 62 are staged into the cache 54.
As shown in FIG.
2, the queue user 52 performs enqueue and dequeue operations to the queue 62.
The enqueue operation places new data at the tail 66 of the queue 62 and therefore does a memory write.
The dequeue operation removes data from the head 64 of the queue 62, and therefore does a memory read.
These memory reads and writes are presented to the cache 54 to fulfill