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Processor microarchitecture for efficient dynamic scheduling and execution of chains of dependent instructions
A processor microarchitecture for efficient dynamic scheduling and execution of chains of dependent instructions is described. The invention includes a predetermined ...
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Lock control for a shared main storage data processing system
The object of the present invention is to provide an improved lock control for sharing a main storage. Another object of the present invention is to provide a lock ...
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Distributed processing memory chip with embedded logic having both data memory and broadcast memory
The present invention provides computer memory chips which include internal computational logic and secondary memory that may be broadcast to in all chips simultaneously ...
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Method and apparatus for locally generating addressing information for a memory access
The present invention overcomes many of the disadvantages of the prior art by providing a system whereby a processor or the like need not provide an address to a memory ...
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System for managing the transfer of data between FIFOs within pool memory and peripherals being programmable with identifications of the FIFOs
Thus, a general purpose of the present invention is to provide a peripheral I/O controller supporting multiple, parallel variable bandwidth data streams over a high ...
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Interface device connected between a LAN and a printer for outputting formatted debug information about the printer to the printer
The aforementioned problems are addressed by the present invention in which formatted debug information is output by a network device to an image forming apparatus to ...
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Asynchronous transfer mode based service consolidation switch
From the foregoing, a need has arisen for a telecommunications switch that integrates a variety of services through an asynchronous transfer mode based operation. In ...
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Queue ordering for memory and I/O transactions in a multiple concurrent transaction computer system
Embodiments of the present invention provide a transaction ordering mechanism for processor-based computing systems which ensures proper ordering of transactions between ...
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Method and apparatus for controlling configuration memory contexts of processing elements in a network of multiple context processing elements
A method and apparatus for providing local control of processing elements in a network of multiple context processing element are provided. According to one aspect of ...
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System and method for queuing of tasks in a multiprocessing system
OF THE INVENTION The block diagram of FIG. 1 illustrates a multi-node network 10 configured as a disk drive controller array. Nodes A and D are data storage nodes that ...
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