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Details
Inventors: Sidman, Steven B.;
Assignee: Sharp Microelectronics Technology, Inc. (Camas, WA); Sharp Kabushiki/Kaisha (Osaka, JP)
Primary Examiner: Lee; Thomas C.
Assistant Examiner: Boortalary; Forood
Attorney, Agent or Firm: Ripma; David C., Maliszewski; Gerald

A system and method is provided for use in register-based CPUs for processing data in the CPU register bank while concurrently loading and unloading data into additional register banks. The additional register banks are then sequentially connected to the CPU datapath for data processing. Interconnections between the various register banks in the CPU and appropriate data buses for performing the load/process/unload functions are controlled by a load/store control logic block which can be a simple state machine processor. The load/store control logic is triggered by a software instruction encountered at the end of particular computational routines during normal program execution. This software instruction replaces the need for separate load and store instructions and their attendant clock cycles. The invention substantially decreases unused data processor time since the arithmetic and logic unit (ALU) can be sequentially connected to register banks which have been pre-loaded with data for processing. The need to stop data processing through the ALU while data is loaded into an unloaded from the CPU register bank is eliminated. A method of register-based CPU concurrent I/O operation is also disclosed.

DETAILED DESCRIPTION The invention relates generally to computers and, more particularly, to the central processing unit (CPU) of a register-based computer.
General purpose register-based computers employ one or more banks of data storage registers within the CPU, where data is temporarily stored during arithmetic or other data processing.
The data storage registers are usually arranged in register banks, also known as register blocks.
The size of the register banks is determined by the internal architecture of the computer and is a matter of design choice.
Data flows into and out of the registers of the CPU through buses which connect with larger computer memory storage units and with the arithmetic and logic unit (ALU) of the CPU.
A 32-bit CPU will typically have 32-bit data buses and 32-bit registers, allowing the data to be moved through the datapath in parallel.
The data storage register banks in a CPU, together with certain other specialized registers for storing instructions and memory address information, the ALU, and the connecting data buses used in data the processing, are collectively called the CPU datapath.
In a register-based CPU, data is moved and processed in accordance with programming instructions from a software decoder and logic control block, which is external to the datapath but is operatively connected to all major elements in the CPU.
Data is retrieved from the computer's main or cache memory and loaded into the register bank of the CPU.
Once the register bank has been loaded, operands in individual registers are processed by the ALU in accordance with program instructions from the logic control block.
For example, the ALU might add or multiply together the contents of two different registers and store the result in a third register location.
Once the computational processing is complete, the data is unloaded from the register bank and sent to main memory or another location in the computer.
Register-based CPUs are flexible and efficient.
Registers speed up processing because data can be quickly supplied to the ALU and stored in other register locations without having to load and store data through the computer's comparatively slower main memory



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