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Multiple thread multiple data predictive coded parallel processing system and method
| Details |
Inventors: Clery, III, William B.;
Assignee: Patton Electronics Co. (Gaithersburg, MD)
Primary Examiner: Donaghue; Larry D.
Assistant Examiner:
Attorney, Agent or Firm:
A parallel processing system or processor has a computing architecture including a plurality of execution units to repeatedly distribute instruction streams within the processor via corresponding buses, and a series of processing units to access the buses and selectively execute the distributed instruction streams. The execution units each retrieve an instruction stream from an associated memory and place the instruction stream on a corresponding bus, while the processing units individually may select and execute any instruction stream placed on the corresponding buses. The processing units autonomously execute conditional instructions (e.g., IF/ENDIF instructions, conditional looping instructions, etc.), whereby an enable flag within the processing unit is utilized to indicate occurrence of conditions specified within a conditional instruction and control selective execution of instructions in response to occurrence of those conditions. An enable stack is utilized to facilitate processing and execution of nested conditional instructions by storing the states of the enable flag for each nested conditional instruction. The parallel processor may further delay placement of selected instruction streams onto corresponding buses until each processing unit selecting a particular instruction stream enters a state to execute that instruction stream. In addition, each execution unit may cease placing an instruction stream onto a corresponding bus in response to no processing units selecting that instruction stream for execution. |
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DETAILED DESCRIPTION Accordingly, it is an object of the present invention to process large quantities of data with a high degree of parallelism via a parallel processor including a computing architecture wherein execution units repeatedly broadcast instruction streams to processing units that individually may select and execute any instruction stream or designated portion thereof broadcasted by the execution units.
It is another object of the present invention to enable a processing unit of a parallel processor to autonomously execute conditional instructions of an instruction stream via inline opcodes (e.
g.
, opcodes contained within the instruction stream), whereby instructions dependent upon occurrence of conditions indicated within a conditional instruction (e.
g.
, instructions contained within a conditional instruction block) are selectively executed in response to a flag that is set to a state in accordance with occurrence of those conditions.
Further, execution of nested conditional instructions may be accomplished via a stack that stores the states of the flag for each nested conditional instruction, whereby instructions dependent upon conditions indicated within a nested conditional instruction (e.
g.
, instructions contained within a nested conditional instruction block) are selectively executed based on the state of the flag stored in the stack for that nested conditional instruction.
Yet another object of the present invention is to execute conditional looping instructions of an instruction stream within a processing unit of a parallel processor by setting a flag to a particular state to terminate execution of a loop in response to occurrence of conditions indicated within a conditional looping instruction, whereby each processing unit of the processor may execute a different quantity of loop iterations during execution of an instruction stream based on the occurrence of those conditions within that processing unit.
Still another object of the present invention is to reduce idle time within particular processing units of a parallel processor resulting from those processing units waiting for processor execution units to broadcast appropriate portions of selected instruction streams (e
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