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Storing frame modification information in a bank in memory
The present invention comprises a method and system for reserving frame modification information in a data storage unit. In one embodiment, a system comprises a ...
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Scratchpad memory
According to one aspect, a integrated circuit includes a random-access memory (RAM) storage and a controller both located on the same semiconductor chip. The controller ...
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Read lock miss control and queue management
According to one aspect of the invention, a method is described of managing memory access to random access memory includes fetching a read lock memory reference request ...
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Architecture for high speed class of service enabled linecard
Introduction The present invention is a linecard architecture that provides packet routing with very low latency. Portions of the linecard operate at line rate, also ...
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Approximated per-flow rate limiting
Overview The present Application discloses a rate limit scheme, using actual flow data rate requirements rather than type/class of service identifiers, that adapts to ...
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Network switch having system for automatically detecting change in network node connection
What is claimed is: 1. A multiport data communication system for transferring data packets between ports, the data communication system comprising: a plurality of ...
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Method and apparatus for reordering packet data units in storage queues for reading and writing memory
The invention is directed to a method and system for reordering data units that are to be written to, or read from, selected locations in a memory. The data units are re-...
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Enqueue operations for multi-buffer packets
Referring to FIG. 1, a network system 10 for processing data packets includes a source 12 of data packets coupled to an input of a network device 14. An output of the ...
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High performance self balancing low cost network switching architecture based on distributed hierarchical shared
The present invention is directed to a communications component for network communications. The communications component comprises a first data port interface supporting ...
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Methods and systems providing fair queuing and priority scheduling to enhance quality of service in a network
According to one embodiment of the present invention, there is provided an Integrated Bandwidth Latency Scheduler apparatus, method and system (collectively referred to ...
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