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 Processor element having a plurality of processors which communicate with each other and selectively use a common bus

Details
Inventors: Kametani, Masatsugu;
Assignee: Hitachi, Ltd. (Tokyo, JP)
Primary Examiner: Kulik; Paul V.
Assistant Examiner:
Attorney, Agent or Firm: Antonelli, Terry Stout & Kraus

A processor for constructing a single processor system or multiprocessor system comprises, within a base processor element constituting the processor, two CPU with associated local memories, a dual-port RAM accessible from said CPUs, and a common bus switch circuit for connecting any one of said CPUs to a common bus shared by said CPUs.

DETAILED DESCRIPTION An object of this invention is to provide a processor capable of improving, with well balanced and efficient qualities, the processing ability of a multiprocessor or single processor system which is suitable for versatile processing.
The above object is achieved by a processor constituted by a base processor element which includes two CPUs with individual associated local memories, a dual-port RAM (DPR) accessible from the CPUs, and a common bus switch circuit which connects one of the CPUs to a common bus shared by the CPUs.
The inventive processor provides a hardware architecture which allows the two CPUs in the base processor element to operate as if they are a single processor.
With attention being paid to the high independency of the control processing system and intelligent processing system based on the data base and sensor information, the control processing system is alloted to the main processing system with the main CPU so that control arithmetics are implemented by the tight-linked parallel processing in unison with other base processor elements, while the intelligent processing system, for dealing with overhead processings including the interrupt process, system management and intelligent process, is alloted to the background processing system of the main CPU and to the background CPU so as to backup the control processing system of the main CPU.
In consequence, the task switching overhead and interrupt events which disturb the parallel processing for the control processing system are eliminated as much as possible, and the two highly independent processing systems are operated in parallel efficiently, whereby the processing ability of the base processor element is virtually doubled by addition of the processing ability of two CPUs, and also in a multiprocessor system where several base processor elements are linked the total processing ability is doubled as compared with the conventional system and the processing ability can be expanded, at well balanced grades between the control processing system and the intelligent processing system as the number of base processor elements is increased



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