Processor microarchitecture for efficient dynamic scheduling and execution of chains of dependent instructions

DETAILED DESCRIPTION A processor microarchitecture for efficient dynamic scheduling and execution of chains of dependent instructions is described.
The invention includes a predetermined number of independent dispatch queues.
The invention also includes a cluster of execution units coupled to each dispatch queue, such that a particular dispatch queue and the corresponding cluster of execution units forms an independent micropipeline.
Chain-building and steering logic coupled to the dispatch queues identifies a consumer instruction which relies on a producer instruction for operands.
The chain-building and steering logic of the invention issues the consumer instruction to the same dispatch queue as the producer instruction that it is dependent upon.
Instructions are issued from each of the dispatch queues to the corresponding cluster of execution units, such that a result of executing the producer instruction is readily available as the operand for the consumer instruction.
In this manner, several independent chains of dependent instructions are executed concurrently.
In one embodiment of the invention, the output of each execution unit in the cluster is routed to the inputs of all execution units in the cluster such that the result of executing an instruction is available to the inputs of the execution units in the cluster for use in executing a subsequent instruction.
Also, in one embodiment, a load/store dispatch queue provides for out-of-order dispatch of load instructions from the load/store dispatch queue, such that if a load or store instruction at the head of the dispatch queue cannot be dispatched, a subsequent load instruction may be dispatched.