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Queue-ordering-for-memory-and-I-O-transactions-in-a-multiple-concurrent-transaction-computer-system

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Queue ordering for memory and I/O transactions in a multiple concurrent transaction computer system

Details

Inventors: Pawlowski, Stephen S.; MacWilliams, Peter D.; Bell, D. Michael;
Assignee: Intel Corporation (Santa Clara, CA)
Primary Examiner: Cabeca; John W.
Assistant Examiner: Tran; Denise
Attorney, Agent or Firm: Kenyon & Kenyon

A transaction ordering mechanism for processor-based computing systems ensures proper ordering of transactions between the processor, I/O and memory subsystems, ensures cache coherence within the computing system, and facilitates concurrence of the transactions so as to enable high-bandwidth, deadlock-free operation. I/O to memory transactions and processor to memory transactions are placed in a memory request queue in the order in which such transactions appear on the processor bus; I/O to memory transactions are placed in an inbound request queue in the order such transactions appear on the I/O bus; and processor to I/O transactions and completions corresponding to split-transaction I/O to memory read transactions are placed in an outbound request queue in the order in which the split-transaction I/O to memory read transactions and the processor to I/O transactions appear on the processor bus.

DETAILED DESCRIPTION Embodiments of the present invention provide a transaction ordering mechanism for processor-based computing systems which ensures proper ordering of transactions between the processor, I/O and memory subsystems, ensures cache coherence within the system, and facilitates concurrence of the transactions so as to enable a high-bandwidth, deadlock-free computer system.
According to an embodiment of the present invention, I/O to memory transactions and processor to memory transactions are placed in a memory request queue in the order in which such transactions appear on the processor bus; I/O to memory transactions are placed in an inbound request queue in the order such transactions appear on the I/O bus; and processor to I/O transactions and completions corresponding to split-transaction I/O to memory read transactions are placed in an outbound request queue in the order the split-transaction I/O to memory read transactions and the processor to I/O transactions appear on the processor bus.

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