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Single chip microcomputer having a dedicated address bus and dedicated data bus for transferring register bank data to and from an on-line RAM
| Details |
Inventors: Nishimura, Akira; Ogawa, Sunao; Yamada, Yasuo; Kanuma, Akira;
Assignee: Kabushiki Kaisha Toshiba (Kawasaki, JP)
Primary Examiner: Donaghue; Larry D.
Assistant Examiner:
Attorney, Agent or Firm: Foley & Lardner
A single chip microcomputer comprises a central processing unit (CPU) 2, a on-chip RAM 3, a on-chip ROM 5, a first bus DBUS for connecting the CPU, RAM, and ROM with one another and transferring data between them, a second bus ABUS for passing address data corresponding to the data passed through the first bus, a third bus SDBUS for connecting the CPU 2 with the RAM 3 and transferring data between them, the number of bits of the third bus SDBUS being larger than that of the first bus DBUS, and a fourth bus BABUS for connecting the CPU 2 with the RAM 3 and passing address data corresponding to the data passed through the third bus SDBUS. The CPU 2 has a data memory RF serving as general purpose registers for providing internal data to the third bus SDBUS, and a bank specifying register BP for holding positional data of a mapping region in the RAM 3 where the contents of the data memory RF are mapped and providing the positional data to the fourth bus BABUS. The RAM 3 has a memory cell array 31, a bank address control circuit 35 connected to the fourth bus BABUS, for generating a real address according to the contents of the bank specifying register BP (BP0, BP1), and a selection circuit 37 for selecting the real address generated by the bank address control circuit 35, or the address provided through the second bus ABUS. |
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DETAILED DESCRIPTION To solve the problems, an object of the invention is to provide a single chip microcomputer employing a register bank method.
This microcomputer efficiently uses chip space and an on-chip RAM and-easily transfers data between different register banks.
According to a first aspect of the invention, a single chip microcomputer comprises (a) a central processing unit (CPU) for processing programs; (b) an on-chip RAM; (c) an on-chip ROM; (d) a first bus for connecting the CPU, RAM, and ROM with one another and transferring data between them; (e) a second bus for passing address data corresponding to the data passed through the first bus; (f) a third bus for connecting the CPU with the RAM and transferring data between them, the number of bits of the third bus being larger than that of the first bus; and (g) a fourth bus for connecting the CPU with the RAM and passing address data corresponding to the data passed through the third bus.
If there is a request for executing a different program, the CPU of the single chip microcomputer suspends a presently executing program, saves data held in the CPU through the third bus into a region of the RAM specified by an address provided through the fourth bus, starts the different program, completely executes the different program, restores the saved data into the CPU through the third bus from the region of the RAM specified by the address provided through the fourth bus, and resumes the suspended program.
The CPU includes (1) a general purpose register set for holding operation data, (2) a program counter for holding the address of a presently executing program, (3) a processor status word register for holding the statuses of the CPU, and (4) a bank specifying register.
When data are saved and restored to and from a register bank defined in the RAM, an address held in the bank specifying register (4) is provided to the fourth bus.
At the same time, the general purpose register set (1), the program counter (2) and processor status word register (3) are selectively connected to the third bus
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