Apparatus and method for handling multiple mergeable misses in a non-blocking cache |
| In light of the above, therefore, according to a broad aspect of the invention, disclosed herein is ... |
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Method and apparatus for packetizing data into a data stream |
| OF A PREFERRED EMBODIMENT Generally, the present invention provides a method and apparatus for ... |
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Scratchpad memory |
| According to one aspect, a integrated circuit includes a random-access memory (RAM) storage and a ... |
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Read lock miss control and queue management |
| According to one aspect of the invention, a method is described of managing memory access to random ... |
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Network device and method of controlling flow of data arranged in frames in a data-based network |
| It is therefore an object of the present invention to enable FIFO filling without incurring the ... |
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Method and apparatus for synchronized message passing using shared resources |
| In accordance with principles of the present invention, to facilitate communication between a first ... |
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System and method for queuing of tasks in a multiprocessing system
| Details |
Inventors: Brady, James Thomas; Finney, Damon W.; Hartung, Michael Howard; Ko, Michael Anthony; Mendelsohn, Noah R.; Menon, Jaishankar Moothedath; Nowlen, David R.;
Assignee: International Business Machines Corporation (Armonk, NY)
Primary Examiner: Banankhah; Majid A.
Assistant Examiner:
Attorney, Agent or Firm: Ohlandt, Greeley, Ruggiero & Perle
A procedure controls execution of priority ordered tasks in a multi-nodel data processing system. The data processing system includes a node with a software-controlled processor and a hardware-configured queue-controller. The queue-controller includes a plurality of priority-ordered queues, each queue listing tasks having an assigned priority equal to a priority order assigned to the queue. The queue-controller responds to a processor generated order to queue a first task for execution, by performing a method which includes the steps of: listing said first task on a first queue having an assigned priority that is equal to a priority of said first task; if a second task is listed on a queue having a higher assigned priority, attempting execution of the second task before execution of the first task; if no tasks are listed on a queue having a higher assigned priority than said first queue, attempting execution of a first listed task in the first queue means; and upon completion of execution of the task or a stalling of execution of the task, attempting execution of a further task on the first queue only if another order has not been issued to place a task on a queue having a higher assigned priority. The method further handles chained subtasks by attempting execution of each subtask of a task in response to the processor generated order; and if execution of any subtask does not complete, attempting execution of another task in lieu of a subtask chained to the subtask that did not complete. |
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DETAILED DESCRIPTION OF THE INVENTION The block diagram of FIG. 1 illustrates a multi-node network 10 configured as a disk drive controller array. Nodes A and D are data storage nodes that connect to coupled disk drives 12, 14 and 16, 18, respectively. A pair of communication interface nodes B and C provide input/output functions to coupled host processors which make use of the data storage facilities of the multi-node network. A cache node E provides temporary storage facilities for both input and output of data transfer functions between network 10 and one or more of the host processors. Multi-node network 10 is expandable by addition of further nodes, all of which are interconnected by an internal communication network 20. Each of nodes A-E is configured from a common node arrangement shown in FIG. 2. Each node includes a node processor 22 that controls the overall functions of the node. Each node further includes a control message "line" 24 for receiving, storing and dispatching control messages and a data message "line" 26 for receiving, storing and dispatching data messages. Control message line 24 comprises a control memory interface module 27 and a dynamic random access memory (DRAM) 28 which serves as a control message memory. Each data message line 26 includes a data buffer interface module 30 and a DRAM 32 for data messages. Data buffer interface module 30 connects to a plurality of device interfaces 34, 36, etc. which, in turn, provide communication to associated disk drives 38, 40, etc. Control messages originating from control memory interface 26, processor 22, etc. enable control of various node actions. As will become apparent from the description below, the architecture of multi-node network 10 is configured to efficiently handle both long data messages that characteristically occur from/to disk drives and a multiplicity of small control messages which are required to enable operation of both the network and individual nodes. Within each node, respective control and data message lines enable segregation of control and data messages and allow their independent processing and transfer to an input/output switch 42 which is provided in each node
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