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 System for flushing queued memory write request corresponding to a queued read request and all prior write requests with counter indicating requests to be flushed

Details
Inventors: Foster, Joseph E.;
Assignee: Compaq Computer Corporation ()
Primary Examiner: Lee; Thomas C.
Assistant Examiner: Wang; Albert
Attorney, Agent or Firm: Daffer; Kevin L. Conley, Rose & Tanyon

A computer is provided having a bus interface unit between a CPU bus and a memory bus. The bus interface unit includes a memory controller and a read/write queue manager. The memory controller dispatches, or removes read requests or write requests from respective read or write requests queues depending on various modes of operation. Typically, the read requests are dispatched or removed either singularly or as a programmed series of read requests prioritized over write requests unless the write request queue is almost full. If the write request queue is almost full, then write request are removed either singularly or in a series before servicing the read request queue. The number of read or write request being removed from their respective queues can be programmed within a configuration register operably coupled to a controller arranged between the read and write request queues. The memory controller determines how many requests will be serviced within possibly a lengthy series of requests. By dispatching like requests (a series of reads followed by a series of writes, etc.) memory bus efficiency and/or pipelining is greatly improved.

DETAILED DESCRIPTION The problems outlined above are in large part solved by a device and method for improving memory bus efficiency.
The device includes an interface unit coupled between a memory requester and the memory.
The memory requester is deemed any device which can seek access (i.
e.
, request) the memory, a suitable memory being asynchronous or synchronous DRAM.
The interface unit is therefore a bus interface unit between the CPU bus and the memory bus, as well as possibly between other busses and the memory bus.
For example, the interface unit provides coupling of a dedicated graphics bus or the PCI bus to the memory bus.
Thus, the interface unit may be considered a north bridge, and the memory requestor comprises an input/output device, such as a disk drive, a display, a keyboard, or any device which can present parallel- or serial-fed addresses and data.
According to one embodiment, the interface unit includes a queue manager.
The queue manager includes logic which performs cross-snooping between a first and second request queue.
The first request queue can be considered a write request queue, whereas the second request queue can be considered a read request queue.
Thus, the memory requester dispatches read and write memory requests to a memory controller via the queue manager.
According to another embodiment, queue snoop logic is coupled within the queue manager between the first and second request queues.
The queue snoop logic helps determine a hit to a request queue, and the location of that hit within the requested queue.
For example, if a read request encounters a hit within the write request queue, then write request within the write request queue (first request queue) must be flushed.
According to yet another embodiment, a controller is coupled to the queue manager.
The memory controller includes logic to service read requests before write requests unless there is a flush requested, or if the write request queue is almost full.
Read requests are normally serviced before write requests



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