System for managing the transfer of data between FIFOs within pool memory and peripherals being programmable with identifications of the FIFOs

DETAILED DESCRIPTION Thus, a general purpose of the present invention is to provide a peripheral I/O controller supporting multiple, parallel variable bandwidth data streams over a high total bandwidth data transfer path established between a central processor and multiple multimedia, network and communications related peripheral devices.
This is achieved in the present invention through a data transfer control system including a pool memory, a plurality of peripheral devices, and a transfer controller.
The pool memory provides for the storage of data in a plurality of FIFOs formed within the pool memory.
The plurality of peripheral devices are coupleable to the pool memory to provide for the transfer of data between programmatically associated FIFOs and peripheral devices.
The transfer controller is coupled to the pool memory and to the peripheral devices for selectively managing the transfer of data between the FIFOs and the peripheral devices.
The transfer controller includes a distributed signaling system coupled to the peripheral devices to permit the broadcast of status information reflective of a transfer of data relative to a predetermined FIFO to the peripheral devices.
A computer system utilizing the multiple parallel digital data stream channel controller of the present invention can thus support the concurrent real-time transfer of a plurality of I/O data streams to and from an auxiliary data processing unit.
The computer system can include a first processing unit including a first memory providing for the storage of a plurality of data streams characterized as each having a respective data transfer rate, a second processing unit providing for the manipulation of data within data segments of the plurality of data streams, and the channel controller coupled between the first and second processing units to provide for the transfer of the plurality of data streams between the first and second processors.
The channel controller provides for the selective transfer of data segments of the plurality of data streams based on the respective data transfer rates of the data streams