System for selectively communicating instructions from memory locations simultaneously or from the same memory locations sequentially to plurality of processing

DETAILED DESCRIPTION Overall System--FIG.
1 In FIG.
1, a high performance, low-cost system 2 is shown for computation-intensive numeric tasks.
The FIG.
1 system processes computation tasks in the numeric processor(NP) computer 3.
The computer 3 typically includes a processing unit(PU) 8 for computation-intensive task, includes an instruction unit(IU) 9 for the fetching, dispatching, and caching of instructions, includes a register multiconnect unit (MCU) 6 for connecting data from and to the processing unit 8, and includes an interface unit(IFU) 23 for passing data to and from the main store 7 over bus 5 and to and from the I/0 24 over bus 4.
In one embodiment, the interface unit 23 is capable of issuing two main store requests per clock for the multiconnect unit 6 and one request per clock for the instruction unit 9.
The computer 3 employs a horizontal architecture for executing an instruction stream, IS, fetched by the instruction unit 9.
The instruction stream includes a number of instructions, I.
sub.
0, I.
sub.
1, I.
sub.
2, .
.
.
, I.
sub.
k, .
.
.
, I.
sub.
(K-1) where each instruction, I.
sub.
k, of the instruction stream IS specifies one or more operations o.
sub.
1.
sup.
k,l, o.
sub.
2.
sup.
k,l, .
.
.
, o.
sub.
n.
sup.
k,l, .
.
.
, o.
sub.
N.
sup.
k,l, to be performed by the processing unit 8.
In one embodiment, the processing unit 8 includes a number, N, of parallel processors, where each processor performs one or more of the operations, o.
sub.
n.
sup.
k,l.
Each instruction from the instruction unit 9 provides source addresses (or source address offsets) for specifying the addresses of operands in the multiconnect unit 6 to be transferred to the processing unit 8.
Each instruction from the instruction unit 9 provides destination addresses (or destination address offsets) for specifying the addresses in the multiconnect unit 6 to which result operands from the processing unit 8 are to be transferred.
The multiconnect unit 6 is a register file where the registers are organized in rows and columns and where the registers are accessed for writing into in rows and are accessed for reading from in columns