System for writing a data value at a starting address to a number of consecutive locations equal to a segment length identifier

DETAILED DESCRIPTION OF THE INVENTION Having summarized various aspects of the present invention, reference will now be made in detail to the description of the invention as illustrated in the drawings.
While the invention will be described in connection with these drawings, there is no intent to limit it to the embodiment or embodiments disclosed therein.
On the contrary, the intent is to cover all alternatives, modifications and equivalents included within the spirit and scope of the invention as defined by the appended claims0.
Reference is now made to FIG.
2, which is a block diagram illustrating a system having a DMA controller 130 that is improved by decode circuitry 154 that is capable of executing a new command, in accordance with the present invention.
As will be appreciated by persons skilled in the art, in addition to the newly-added command, which will be described below, the DMA controller 130 has a certain fundamental architecture and operational circuitry.
Illustrating this circuitry within the first DMA controller 130, the functional circuitry inherent in each of the DMA controllers may be illustrated as comprising a DMA engine 150, DMA control 152, decode circuitry 154, and a plurality of registers 156.
In one embodiment, the DMA engine 150 may be implemented as a state machine, which interfaces with all external signaling.
In this regard, the DMA engine 150 interfaces with external circuitry to receive, for example, Acknowledgment signaling and generate, for example, Request signaling.
It also both receives and generates the requisite address and data signals for the bus 118.
The control portion of the circuitry 152 may also be implemented in a state machine, which interfaces among the DMA engine 150, decode circuitry 154, and internal DMA registers 156.
In a preferred embodiment, the registers 156 may include, among others, a configuration register, a command register, a start address register, a data length register, etc.
When a processor, or other external circuit device initiates the DMA process, as described above, it instructs the DMA controller as to the length of the block of data to be transferred, as well as the starting address for the transfer