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 Time-division switching circuit transforming data formats

Details
Inventors: Kawai, Yoshio;
Assignee: Fujitsu Limited (Kawasaki, JP)
Primary Examiner: Olms; Douglas W.
Assistant Examiner: Hsu; Alpus H.
Attorney, Agent or Firm: Staas & Halsey

A time-division switching circuit for exchanging a time slot with another time slot in one cycle of time-division multiplexed data where the above one cycle of data comprises a plurality of time-division multiplexed data respectively having a different data formats. The switching circuit comprises: a data buffer memory a successive address generating circuit for outputting successive writing or reading addresses; an address control memory for holding reading or writing addresses; and an address setting control circuit for setting the addresses of the address control memory. The setting of the above addresses are carried out so that there are simultaneously performed both the exchanges of time slots within each time-division multiplexed data among the above plurality of time-division multiplexed data, and also the exchanges of time slots across different time-division multiplexed data among the above plurality of time-division multiplexed data for transforming a format of data in one of the above different time-division multiplexed data to another format in another of the above different time-division multiplexed data.

DETAILED DESCRIPTION An object of the present invention is to provide a time-division switching circuit for exchanging a time slot with another time slot in one cycle of time-division multiplexed data where the above one cycle of data comprises a plurality of time-division multiplexed data each having a different data format, with a reduced hardware size, a reduced delay time, and simple control.
According to the present invention, there is provided a time-division switching circuit for exchanging a time slot with another time slot in one cycle of time-division multiplexed data, where the above one cycle of data comprises a plurality of time-division multiplexed data each having a different data format.
The time-division switching circuit comprises: a data buffer memory; a successive address generating circuit; an address control memory; and an address setting control circuit.
The data buffer memory holds the above one cycle of time-division multiplexed data.
The successive address generating circuit generates successive addresses to successively write all the time slots of each cycle of time-division multiplexed data in the above data buffer memory, or to successively read the time slots held in the data buffer memory.
The address control memory holds addresses for reading the above data held in the above data buffer memory in such an order that the above exchange of time slots is realized when successive addresses are applied to the address control memory for the reading, or holds addresses for writing all the time slots of each cycle of time-division multiplexed data in the data buffer memory in such an order that the above exchange of time slots is realized when the time slots held in the data buffer memory are successively read out by the successive addresses from the successive address generating circuit.
The address setting control circuit sets the above addresses for reading or writing in the above address control memory, where the setting of the above addresses is carried out so that both the exchanges of time slots within each time-division multiplexed data among the above plurality of time-division multiplexed data, and the exchanges of time slots across different time-division multiplexed data among the above plurality of time-division multiplexed data for transforming a format of data in one of the above different time-division multiplexed data to another format in another of the above different time-division multiplexed data, are simultaneously carried out



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