Bus arbitration and resource management for concurrent vector signal processor architecture
These and other objects, features and advantages are achieved by the concurrent vector signal processor architecture disclosed herein. To support concurrent operation of the concurrent vector signal p... Read More
Inventors: Genusov, Alexander; Friedlander, Ram B.; Feldman, Peter; Jaliff, Ricardo;, Assignee: Zoran Corporation (Santa Clara, CA) |
Dual-array register file with overlapping window registers
OF THE PREFERRED EMBODIMENTS The following description will successively discuss the respective register files according to five embodiments of the present invention with reference to the attached dr... Read More
Inventors: Ozaki, Shinji;, Assignee: Matsushita Electric Industrial Co., Ltd. (Kadoma, JP) |
Content addressable memory implementation with random access memory
OF THE INVENTION In the following, the invention is described in detail with reference to the drawings and the prior ad. The addresses of the memory locations of the shown random access memories corr... Read More
Inventors: Heddes, Mattheus C. A.;, Assignee: International Business Machines Corporation (Armonk, NY) |
Access to unsubscribed features
FIG. 1 is a block diagram illustrating the basic operation of applicant's invention. Station 1 is one of many stations connected to local switching system 5. In FIG. 1, station 1 is connected at term... Read More
Inventors: Andruska, Donald L.; Majeti, Venkata C.;, Assignee: AT&T Corp. (Murray Hill, NJ) |
Processor element having a plurality of processors which communicate with each other and selectively use a common bus
An object of this invention is to provide a processor capable of improving, with well balanced and efficient qualities, the processing ability of a multiprocessor or single processor system which is s... Read More
Inventors: Kametani, Masatsugu;, Assignee: Hitachi, Ltd. (Tokyo, JP) |
Channel allocation system for distributed digital switching network
OF THE DRAWINGS A. System Layout FIG. 1 illustrates a switching network for interconnecting various types of voice or data equipment and telephone lines, indicated generally as units 11-15 in accorda... Read More
Inventors: Cotton, John M.; Pieper, Gary V.;, Assignee: IPC Information Systems, Inc. (Stamford, CT) |
Memory controller with priority queues
In an illustrative embodiment of the invention, a memory controller receives reads, memory writes, and cache writes. A pending read is selected and issued to memory. When a response is received from m... Read More
Inventors: Williams, James B.;, Assignee: Hewlett-Packard Co. (Palo Alto, CA) |
Multiple register bank system for concurrent I/O operation in a CPU datapath
The invention relates generally to computers and, more particularly, to the central processing unit (CPU) of a register-based computer. General purpose register-based computers employ one or more bank... Read More
Inventors: Sidman, Steven B.;, Assignee: Sharp Microelectronics Technology, Inc. (Camas, WA); Sharp Kabushiki/Kaisha (Osaka, JP) |
Processor microarchitecture for efficient dynamic scheduling and execution of chains of dependent instructions
A processor microarchitecture for efficient dynamic scheduling and execution of chains of dependent instructions is described. The invention includes a predetermined number of independent dispatch que... Read More
Inventors: Sharangpani, Harshvardhan P.; Fielden, Kent G.; Mulder, Hans J.;, Assignee: Intel Corporation (Santa Clara, CA) |
Lock control for a shared main storage data processing system
The object of the present invention is to provide an improved lock control for sharing a main storage. Another object of the present invention is to provide a lock control which operates locally so as... Read More
Inventors: Matsumoto, Kazuya;, Assignee: NEC Corporation (Tokyo, JP) |
Distributed processing memory chip with embedded logic having both data memory and broadcast memory
The present invention provides computer memory chips which include internal computational logic and secondary memory that may be broadcast to in all chips simultaneously and systems with such memories... Read More
Inventors: Mahant-Shetti, Shivaling S.; Smith, Derek J.; Pawate, Basavaraj I.; Doddington, George R.; Bean, Warren L.; Harward, Mark G.; Aton, Thomas J.;, Assignee: Texas Instruments Incorporated (Dallas, TX) |
Method and apparatus for locally generating addressing information for a memory access
The present invention overcomes many of the disadvantages of the prior art by providing a system whereby a processor or the like need not provide an address to a memory unit for each read and/or write... Read More
Inventors: Byers, Larry L.; Robeck, Gary R.; Brunmeier, Terry J.;, Assignee: Unisys Corporation (Blue Bell, PA) |
System for managing the transfer of data between FIFOs within pool memory and peripherals being programmable with identifications of the FIFOs
Thus, a general purpose of the present invention is to provide a peripheral I/O controller supporting multiple, parallel variable bandwidth data streams over a high total bandwidth data transfer path ... Read More
Inventors: Lewis, Adrian; Gifford, James K.; Begur, Sridhar; Spencer, Donald J.; Kilbourn, Thomas E.; Gochnauer, Daniel B.;, Assignee: Diamond Multimedia Systems, Inc. (San Jose, CA) |
Interface device connected between a LAN and a printer for outputting formatted debug information about the printer to the printer
The aforementioned problems are addressed by the present invention in which formatted debug information is output by a network device to an image forming apparatus to which the network device is conne... Read More
Inventors: Barrett, Lorraine F.; Russell, William C.; Danknick, Daniel A.;, Assignee: Canon Information Systems, Inc. (Irvine, CA) |
Asynchronous transfer mode based service consolidation switch
From the foregoing, a need has arisen for a telecommunications switch that integrates a variety of services through an asynchronous transfer mode based operation. In accordance with the present invent... Read More
Inventors: Hauser, Stephen A.; Caldara, Stephen A.; Manning, Thomas A.; McClure, Robert B.;, Assignee: Fujitsu Network Communications, Inc. (Richardson, TX); Fujitsu Limited (Kawasaki, JP) |
Queue ordering for memory and I/O transactions in a multiple concurrent transaction computer system
Embodiments of the present invention provide a transaction ordering mechanism for processor-based computing systems which ensures proper ordering of transactions between the processor, I/O and memory ... Read More
Inventors: Pawlowski, Stephen S.; MacWilliams, Peter D.; Bell, D. Michael;, Assignee: Intel Corporation (Santa Clara, CA) |
Method and apparatus for controlling configuration memory contexts of processing elements in a network of multiple context processing elements
A method and apparatus for providing local control of processing elements in a network of multiple context processing element are provided. According to one aspect of the invention, a multiple context... Read More
Inventors: Mirsky, Ethan; French, Robert; Eslick, Ian;, Assignee: Silicon Spice (Mountain View, CA) |
System and method for queuing of tasks in a multiprocessing system
OF THE INVENTION The block diagram of FIG. 1 illustrates a multi-node network 10 configured as a disk drive controller array. Nodes A and D are data storage nodes that connect to coupled disk drives ... Read More
Inventors: Brady, James Thomas; Finney, Damon W.; Hartung, Michael Howard; Ko, Michael Anthony; Mendelsohn, Noah R.; Menon, Jaishankar Moothedath; Nowlen, David R.;, Assignee: International Business Machines Corporation (Armonk, NY) |
System for flushing queued memory write request corresponding to a queued read request and all prior write requests with counter indicating requests to be flushed
The problems outlined above are in large part solved by a device and method for improving memory bus efficiency. The device includes an interface unit coupled between a memory requester and the memory... Read More
Inventors: Foster, Joseph E.;, Assignee: Compaq Computer Corporation () |
Load and store unit for a vector processor
A load/store unit within a vector processor services memory requests to load or store vectors (multiple data elements of a substantially similar type). Such an apparatus provides the advantage of hand... Read More
Inventors: Nguyen, Le Trong; Park, Heonchul; Cho, Seong Rai;, Assignee: Samsung Electronics Co., Ltd. (Seoul, KR) |
Smart buffer size adaptation apparatus and method
The present invention is directed toward a data communication system, comprising a frame processing device having a driver and a processor for executing the driver; a LAN controller for receiving LAN ... Read More
Inventors: Nogradi, Christopher I.;, Assignee: Milgo Solutions, Inc. (Sunrise, FL) |
Creation and use of control information associated with packetized network data by protocol drivers and device drivers
OF THE PREFERRED EMBODIMENTS As used herein, the term "software component" refers to any set of executable instructions separately cognisable to an operating system that manages a computer system. Ex... Read More
Inventors: Hyder, Jameel; Brandon, Kyle;, Assignee: Microsoft Corporation (Redmond, WA) |
Reconfigurable computing architecture for providing pipelined data paths
The present invention is a reconfigurable data path whose functionality is controlled by a combination of static and dynamic control, wherein the configuration is referred to as static control, and in... Read More
Inventors: Ebeling, William Henry Carl; Cronquist, Darren Charles; Franklin, Paul David;, Assignee: University of Washington (Seattle, WA) |
Multiple thread multiple data predictive coded parallel processing system and method
Accordingly, it is an object of the present invention to process large quantities of data with a high degree of parallelism via a parallel processor including a computing architecture wherein executio... Read More
Inventors: Clery, III, William B.;, Assignee: Patton Electronics Co. (Gaithersburg, MD) |
Distributed data dependency stall mechanism
The invention resides in allowing each probe queue in a multiprocessor computer system to be individually stalled when a probe message, that targets data not yet stored in an associated cache or victi... Read More
Inventors: Van Doren, Stephen; Razdan, Rahul;, Assignee: Compaq Computer Corporation (Houston, TX) |
Method and apparatus for arbitrating between command streams
The present invention provides a method and apparatus for arbitrating between command streams. In the following description, numerous specific details such as command priorities and types, queue arra... Read More
Inventors: Harriman, David J.; Langendorf, Brian K.; Ajanovic, Jasmin;, Assignee: Intel Corporation (Santa Clara, CA) |
Computer with remote wake up and transmission of a status packet when the computer fails a self test
The failure of a component of a computer upon the awakening of the computer is brought to the attention of proper authorities by transmitting a status packet onto a network. An apparatus for use in a ... Read More
Inventors: Klein, Philippe; Ben-Michael, Simoni; Menachem, Avraham; Shvimmer, Sarit;, Assignee: Digital Equipment Corporation (Maynard, MA) |
Low power, high speed communications bus
The solution to the problem of data communication between a CPU and a memory where the internal speed of the CPU is mismatched to the access speed of the memory is a high speed bus in accordance with ... Read More
Inventors: Sherman, David L.;, Assignee: Gigabus, Inc. (Fremont, CA) |
Apparatus and method for handling multiple mergeable misses in a non-blocking cache
In light of the above, therefore, according to a broad aspect of the invention, disclosed herein is a multi-level cache and method for merging cache misses which access the same line of a non-blocking... Read More
Inventors: Mehrotra, Sharad; Hetherington, Ricky C.; Wong, Michelle L.;, Assignee: Sun Microsystems, Inc. (Palo Alto, CA) |
Method and apparatus for maintaining one or more queues of elements such as commands using one or more token queues
The present invention provides a method and apparatus for maintaining one or more queues of varying types of elements. In the following description, numerous specific details such as command types, c... Read More
Inventors: Harriman, David J.;, Assignee: Intel Corporation (Santa Clara, CA) |
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