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Results: 31-60 of 4232
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Method and system for executing a program within a multiscalar processor by processing linked thread descriptors
The multiscalar processing paradigm disclosed herein overcomes numerous deficiencies of the previously proposed multiscalar paradigm through improvements to both the multiscalar hardware and software... Read More
Inventors: Kahle, James A.; Mallick, Soummya; McDonald, Robert G.; Swarthout, Edward L.;, Assignee: International Business Machines Corporation (Armonk, NY) |
Single chip microcomputer having a dedicated address bus and dedicated data bus for transferring register bank data to and from an on-line RAM
To solve the problems, an object of the invention is to provide a single chip microcomputer employing a register bank method. This microcomputer efficiently uses chip space and an on-chip RAM and-easi... Read More
Inventors: Nishimura, Akira; Ogawa, Sunao; Yamada, Yasuo; Kanuma, Akira;, Assignee: Kabushiki Kaisha Toshiba (Kawasaki, JP) |
Method and apparatus for packetizing data into a data stream
OF A PREFERRED EMBODIMENT Generally, the present invention provides a method and apparatus for packetizing data. Such processing begins by determining the bit time occurrence for retrieval of at leas... Read More
Inventors: O'Loughlin, Gareth P.; Patoine, Michel J. P.; Smail, J. Morgan;, Assignee: Alcatel Canada Inc. (Kanata, CA) |
Scratchpad memory
According to one aspect, a integrated circuit includes a random-access memory (RAM) storage and a controller both located on the same semiconductor chip. The controller is coupled to read data from an... Read More
Inventors: Wolrich, Gilbert; Bernstein, Debra; Adiletta, Matthew;, Assignee: Intel Corporation (Santa Clara, CA) |
Read lock miss control and queue management
According to one aspect of the invention, a method is described of managing memory access to random access memory includes fetching a read lock memory reference request and placing the read lock memor... Read More
Inventors: Wolrich, Gilbert; Cutter, Daniel; Wheeler, William; Adiletta, Matthew J.; Bernstein, Debra;, Assignee: Intel Corporation (Santa Clara, CA) |
Computer program product used for exchange and transfer of data having a siga vector and utilizing a queued direct input-output device
A computer program product and storage device used for exchange and transfer of data in a network computing system having a main storage capable of connecting to at least one application server and an... Read More
Inventors: Glassen, Steven G.; Oakes, Kenneth J.; Ratcliff, Bruce H.; Stagg, Arthur J.;, Assignee: International Business Machines Corporation (Armonk, NY) |
Network device and method of controlling flow of data arranged in frames in a data-based network
It is therefore an object of the present invention to enable FIFO filling without incurring the same overhead expenses as required for a previous watermark interrupt command. It is still another objec... Read More
Inventors: Kasper, Christian D.;, Assignee: STMicroelectronics, Inc. (Carrollton, TX) |
Method and apparatus for synchronized message passing using shared resources
In accordance with principles of the present invention, to facilitate communication between a first and second process, access to shared resources is synchronized through discipline imposed upon updat... Read More
Inventors: Harter, Jr., Paul Karl; Fraser, Jr., James Ian;, Assignee: Compaq Information Technologies Group, L.P. (Houston, TX) |
Method and apparatus for network interface card load balancing and port aggregation
Broadly speaking, the present invention fills these needs by providing methods and apparatus for increasing throughput in a load balancing manner over a multi-port NIC. Each port of the multi-port NIC... Read More
Inventors: Latif, Faisal; Sharma, Pramod; Saya, Suleman; Kuhfeld, Jim J.;, Assignee: Adaptec, Inc. (Milpitas, CA) |
System for writing a data value at a starting address to a number of consecutive locations equal to a segment length identifier
OF THE INVENTION Having summarized various aspects of the present invention, reference will now be made in detail to the description of the invention as illustrated in the drawings. While the inventi... Read More
Inventors: Habot, Ronen;, Assignee: Globespan, Inc. (Red Bank, NJ) |
Asynchronous transfer mode based service consolidation switch
From the foregoing, a need has arisen for a telecommunications switch that integrates a variety of services through an asynchronous transfer mode based operation. In accordance with the present invent... Read More
Inventors: Hauser, Stephen A.; Caldara, Stephen A.; Manning, Thomas A.;, Assignee: Fujitsu Network Communications, Inc. (Richardson, TX); Fujitsu Limited (Kanagawa-ken, JP) |
Network switch with a multiple bus structure and a bridge interface for transferring network data between different buses
A network switch according to the present invention includes a plurality of first network ports, a plurality of second network ports, a first bus coupled to the first network ports operating according... Read More
Inventors: Witkowski, Michael L.; Chandler, Gregory T.; Khan, Mohammad A.; Kotzur, Gary B.; Mayer, Dale J.; Walker, William J.;, Assignee: Compaq Computer Corporation (Houston, TX) |
Method, system, and program for managing requests to a cache using flags to queue and dequeue data in a buffer
OF THE PREFERRED EMBODIMENTS In the following description, reference is made to the accompanying drawings which form a part hereof and which illustrate several embodiments of the present invention. I... Read More
Inventors: Slane, Albert Alfonse;, Assignee: International Business Machines Corporation (Armonk, NY) |
High-speed data bus for network switching
The specification will be organized as follows: 1. BlazePath.TM./BlazeFire.TM. Architecture/Chip Set 2. Header "Canonicalization" and Packet "Cellularization" 3. BlazeWire.TM. High-Speed MAC Bus 4. D... Read More
Inventors: Poole, Nigel T.;, Assignee: Top Layer Networks, Inc. (Westboro, MA) |
Method and apparatus for data buffer management in a communications switch
OF A PREFERRED EMBODIMENT OF THE INVENTION Generally, the present invention provides a method and apparatus for buffering data cells in a queuing element included in the output buffer of a data commu... Read More
Inventors: Janoska, Mark William; Heller, Albert D.; Pezeshki-Esfahani, Hossain;, Assignee: Alcatel Canada Inc. (Kanata, CA) |
Handling contiguous memory references in a multi-queue system
What is claimed is: 1. A controller for a random access memory comprises: control logic, including an arbiter that detects a status of outstanding memory references to select a memory reference from o... Read More
Inventors: Wolrich, Gilbert; Bernstein, Debra; Adiletta, Matthew J.; Wheeler, William;, Assignee: Intel Corporation (Santa Clara, CA) |
Communication between processors
Referring to FIG. 1, a computer system 26 includes two processors 1, 2. Each processor 1, 2 has a corresponding static random access memory (SRAM) 21, 22 for storing data that needs to be accessed wi... Read More
Inventors: Wolrich, Gilbert; Bernstein, Debra; Adiletta, Matthew J.;, Assignee: Intel Corporation (Santa Clara, CA) |
Optimizations to receive packet status from fifo bus
According to one aspect of the invention, a method is described of receiving bytes of data from a media device includes issuing N consecutive requests, each for M bytes, to the media device and receiv... Read More
Inventors: Wolrich, Gilbert; Bernstein, Debra; Adiletta, Matthew J.;, Assignee: Intel Corporation (Santa Clara, CA) |
Storing frame modification information in a bank in memory
The present invention comprises a method and system for reserving frame modification information in a data storage unit. In one embodiment, a system comprises a processor configured to process frames... Read More
Inventors: Calvignac, Jean Louis; Heddes, Marco C.; Logan, Joseph Franklin; Verplanken, Fabrice Jean;, Assignee: International Business Machines Corporation (Armonk, NY) |
Scratchpad memory
According to one aspect, a integrated circuit includes a random-access memory (RAM) storage and a controller both located on the same semiconductor chip. The controller is coupled to read data from an... Read More
Inventors: Wolrich, Gilbert; Bernstein, Debra; Adiletta, Matthew;, Assignee: Intel Corporation (Santa Clara, CA) |
Read lock miss control and queue management
According to one aspect of the invention, a method is described of managing memory access to random access memory includes fetching a read lock memory reference request and placing the read lock memor... Read More
Inventors: Wolrich, Gilbert; Cutter, Daniel; Wheeler, William; Adiletta, Matthew J.; Bernstein, Debra;, Assignee: Intel Corporation (Santa Clara, CA) |
Architecture for high speed class of service enabled linecard
Introduction The present invention is a linecard architecture that provides packet routing with very low latency. Portions of the linecard operate at line rate, also referred to as "wire rate" in the... Read More
Inventors: Wilford, Bruce; Dan, Yie-Fong;, Assignee: Cisco Technology, Inc. (San Jose, CA) |
Approximated per-flow rate limiting
Overview The present Application discloses a rate limit scheme, using actual flow data rate requirements rather than type/class of service identifiers, that adapts to varying traffic. This scheme pre... Read More
Inventors: Cheriton, David R.;, Assignee: Cisco Technology, Inc. (San Jose, CA) |
Network switch having system for automatically detecting change in network node connection
What is claimed is: 1. A multiport data communication system for transferring data packets between ports, the data communication system comprising: a plurality of receive ports for receiving data pack... Read More
Inventors: Chiang, John; Merchant, Shashank; Williams, Robert;, Assignee: Advanced Micro Devices, Inc. (Sunnyvale, CA) |
Method and apparatus for reordering packet data units in storage queues for reading and writing memory
The invention is directed to a method and system for reordering data units that are to be written to, or read from, selected locations in a memory. The data units are re-ordered so that an order of ac... Read More
Inventors: O'Grady, Robert; Tran, Sonny N.; Dan, Yie-Fong; Wilford, Bruce;, Assignee: Cisco Technology, Inc. (San Jose, CA) |
Enqueue operations for multi-buffer packets
Referring to FIG. 1, a network system 10 for processing data packets includes a source 12 of data packets coupled to an input of a network device 14. An output of the network device 14 is coupled to ... Read More
Inventors: Wolrich, Gilbert; Rosenbluth, Mark B.; Bernstein, Debra;, Assignee: Intel Corporation (Santa Clara, CA) |
High performance self balancing low cost network switching architecture based on distributed hierarchical shared
The present invention is directed to a communications component for network communications. The communications component comprises a first data port interface supporting a plurality of data ports tran... Read More
Inventors: Kadambi, Shiri; Ambe, Shekhar;, Assignee: Broadcom Corporation (Irvine, CA) |
Methods and systems providing fair queuing and priority scheduling to enhance quality of service in a network
According to one embodiment of the present invention, there is provided an Integrated Bandwidth Latency Scheduler apparatus, method and system (collectively referred to herein as IBLS) that combines F... Read More
Inventors: Mysore, Manamohan D.; Pagan, Florence C.; Short, Joel E.; Bhagavath, Vijay Krishna;, Assignee: Nomadix, Inc. (Westlake Village, CA) |
Method for aging table entries in a table supporting multi-key searches
The invention is for use with a table containing a plurality of data entries, each of the data entries made up of a string of data. Each string of data contains a first address addressable by a first ... Read More
Inventors: Viswanath, Somnath;, Assignee: Advanced Micro Devices, Inc. (Sunnyvale, CA) |
Enhancing performance by pre-fetching and caching data directly in a communication processor's register set
OF THE INVENTION Various aspects of packet processing integrated circuits are discussed in U.S. Pat. No. 5,748,630, entitled "ASYNCHRONOUS TRANSFER MODE CELL PROCESSING WITH LOAD MULTIPLE INSTRUCTION... Read More
Inventors: Galbi, Duane E.; Snyder, II, Wilson P.; Lussier, Daniel J.;, Assignee: Mindspeed Technologies, Inc. (Newport Beach, CA) |
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