Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices

DETAILED DESCRIPTION It is a first object of the present invention to synchronize clock signals among a plularity of information processing units inside an information processor.
It is a second object of the present invention to supply each information processing unit with a clock signal having a minimized clock skew and a precise duty cycle.
It is a third object of the present invention to avoid the supply of a high-speed clock signal from the outside of an information processing unit.
It is a fourth object of the present invention to reduce the clock skew, the clock delay time and the clock rise and fall time inside semiconductor integrated circuit devices having logic circuits controlled by clock signals.
It is a fifth object of the present invention to provide a clock driver which is capable of coping with the need for high-speed and high-frequency clock signals.
One feature of the present invention resides in an information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each of the information processing units comprises a clock generating means for generating at least one second clock signal K.
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1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.
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1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.
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1.
The clock signal K.
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1 that is generated inside each information processing unit is phase-locked with the original clock signal K.
Accordingly, the clock signal K.
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1 inside a certain information processing unit can be phase-locked with the clock signal K.
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1 inside another information processing unit through the original clock signal K.
Since each information processing unit incorporates a clock generating means for generating at least one second clock signal K