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Peer-to-peer cache moves in a multiprocessor data processing system
| Details |
Inventors: Freerksen, Donald Lee; Lippert, Gary Michael; Irish, John D.;
Assignee: International Business Machines Corporation (Armonk, NY)
Primary Examiner: Coleman; Eric
Assistant Examiner:
Attorney, Agent or Firm: Wood, Herron & Evans
A memory cache system is used in a multiprocessor environment. The first processor accesses data using a first level 1 cache, and the second processor accesses data using a second level 1 cache. A storage control circuit is positioned between the first and second level 1 caches and a level 2 cache and main memory. The level 2 cache maintains copies of data in main storage and further maintains an indication of those level 1 caches having copies of data and whether those copies have been modified. When a processor accesses data that is not resident in the connected level 1 cache, a request is delivered to the level 2 cache for this data. The level 2 cache then determines whether it can return a copy of the data to the level 1 cache or must access the data from main memory. Also, when the level 2 cache determines that another level 1 cache is storing a modified copy of the data, the level 2 cache returns to the storage control circuit a pointer to the level 1 cache having the modified copy of the data; the storage control circuit then causes the level 1 cache having a modified copy of the data, to transfer the modified data to the requesting level 1 cache without returning the data to the level 2 cache or main memory. This ameliorates the effects of repeated writes to the same data by the multiple processors. |
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DETAILED DESCRIPTION In accordance with principles of the present invention, a memory cache system is used in a multiprocessor environment having first and second processors.
The first processor accesses data using a first cache and shared lower level storage, and the second processor accesses data using a second cache and the shared lower level storage.
A storage control circuit is positioned between the first and second caches and the lower level storage.
When the first or second processor accesses data that is not resident in the respective first or second cache, a request is delivered to the storage control circuit for this data.
To ameliorate the effect of repeated writes to the same data by the first and second processors, when the storage control circuit receives a request for data from the first cache, and that data has been modified by the second processor and is stored in modified form in the second cache, the storage control circuit causes the second cache to transfer the modified data to the first cache without returning the data to the shared lower level storage.
In the specific embodiment described below, the shared lower level storage system includes a lower level or level 2 cache, as compared to the first and second caches which are level 1 caches.
The level 2 cache maintains copies of data in main storage and further maintaining an indication of those level 1 caches having copies of data and whether those copies have been modified.
When a request for data from a level 1 cache is received by the storage control circuit, this request is delivered to the level 2 cache, which determines whether another level 1 cache is storing a modified copy of the data, and if so the level 2 cache returns to the storage control circuit a pointer to the level 1 cache having the modified copy of the data.
The level 2 cache maintains data in a queue from least to most recently used.
When a request for data from a level 1 cache is satisfied by returning a pointer to another level 1 cache, the level 2 queue is updated to identify the copy of that data in the level 2 cache as most recently used
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Finance 
