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System and apparatus for partially flushing cache memory
| Details |
Inventors: Rahman, Saba; Mudgett, Dan S.; Andrade, Victor F.;
Assignee: Advanced Micro Devices, Inc. (Sunnyvale, CA)
Primary Examiner: Chan; Eddie P.
Assistant Examiner: Ellis; Kevin L.
Attorney, Agent or Firm: Conley, Rose & Tayon, Kivlin; B. Noel
A computer system is disclosed for selectively invalidating the contents of cache memory in response to the removal, modification, or disabling of system resources, such as for example, an external memory device. The computer system includes an interface unit which defines an address window for the particular system resource. The address window is implemented through the use of a lower address register and an upper address register, which are loaded in response to a lower and upper enable address signal. An upper comparator compares each tag address with the upper address register value, and a lower comparator compares each tag address with the lower address register value. If the tag address falls within the window, it is flushed by the generation of appropriate control signal. In an alternative embodiment, the present invention can be implemented through software by instructions in microcode. As yet another alternative, the present invention can be implemented by comparing each memory window address value with the stored tag address in the cache. |
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DETAILED DESCRIPTION The present invention solves the shortcomings and deficiencies of the prior art by constructing a computer system capable of selectively flushing a cache memory.
In the preferred embodiment, a processing unit contained in the computer system compares cache memory tag address values with the addresses assigned to an external memory device.
The processing unit includes registers which provide a window of address values available in the external memory device.
The registers preferably include a lower start address register and an upper end address register, which, when initiated, are loaded with the start and end values of the external memory addresses, respectively.
A lower and upper comparator compares each tag address from the cache memory with the values in the lower and upper registers, respectively.
If a tag address is found which has a value within the window defined by the upper and lower address registers, it is invalidated and the corresponding data is flushed from the cache memory.
As an alternative to this hardware implementation of the present invention, instructions may be written in microcode to perform a similar process.
Thus, the start and end address values of the external memory device would be fetched and compared through software routines with the tag address values.
An instruction to flush a particular line in the cache memory then would be generated by the processor in response to an affirmative comparison.
In yet another alternative embodiment, a bus interface unit is provided which contains a memory map of the available addresses in an external memory device.
In response to removal of the external memory from the computer system, the bus interface unit sequentially cycles through each available external memory address in the memory map, requesting the cache controller to compare the memory address to tag addresses in cache memory.
If a match for the external memory address is found in the tag address, the cache memory contents corresponding to that tag address are invalidated
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Finance 
