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Method of fabricating high-conductivity silicide-on-polysilicon structures for MOS devices
| Details |
Inventors: Fraser, David B.; Kinsbron, Eliezer; Vratny, Frederick;
Assignee: Bell Telephone Laboratories, Incorporated (Murray Hill, NJ)
Primary Examiner: Lawrence; Evan K.
Assistant Examiner:
Attorney, Agent or Firm: Canepa; Lucian C.
It is known to deposit a refractory metal silicide on a polysilicon gate layer to form a low-resistivity composite structure. For VLSI MOS devices, very-high-resolution patterning of the composite structure is required. In accordance with this invention, a silicide pattern is formed on polysilicon by a lift-off technique. In turn, the patterned silicide is utilized as a mask for anisotropic etching of the underlying polysilicon. High-conductivity composite silicide-on-polysilicon gate structures for VLSI MOS devices are thereby achieved. |
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DETAILED DESCRIPTION In accordance with the principles of the present invention, a high-resolution silicide-on-polysilicon structure is formed in a VLSI device in a fabrication sequence that includes a so-called lift-off step. To implement the lift-off step, it is particularly advantageous to form a pattern in the device to be fabricated by employing the process described by J. M. Moran and D. Maydan in "High Resolution, Steep Profile, Resist Patterns", in The Bell System Technical Journal, volume 58, No. 5, May-June 1979, pp. 1027-1036. This process is also described in a commonly assigned copending U. S. application of D. B. Fraser, D. Maydan and J. M. Moran designated Ser. No. 941,369, filed Sept. 11, 1978, now U. S. Pat. No. 4,244,799, issued Jan. 13, 1981. The described process, which is sometimes referred to as the trilevel process, is characterized by submicron resolution with excellent linewidth control and step coverage. FIG. 1 depicts a high-resolution steep-profile pattern made in accordance with the aforespecified trilevel processing sequence. The depicted pattern is shown formed in a relatively thick layer 10 of a hardened organic material. By way of example, the patterned layer 10 is approximately 1. 5 micrometers (. mu. m) thick. Typical materials therefor will be specified below. Deposited on top of the layer 10 is a so-called intermediate masking layer 12 approximately 0. 12 . mu. m thick and made, for example, of plasma-deposited silicon dioxide. In prior steps of the standard trilevel process, the layer 12 was selectively etched using a thin overlying high-resolution resist pattern (not shown) as the mask therefor. The pattern in the relatively thin layer 12 was then transferred into the underlying layer 10 to form a corresponding pattern, by conventional techniques known in the art. Illustrative organic materials from which to form the layer 12 shown in FIG. 1 include a polyimide designated PIQ made by Hitachi Ltd. , Tokyo, Japan, a polyimide designated Pyralin made by E. I. duPont de Nemours and Co
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