DETAILED DESCRIPTION It is an object of the invention to provide a voltage multiplier circuit incorporating a more effective voltage multiplication, where the output voltage is not limited by the back-gate bias effect or by the level of the supply voltage, and where conduction of the parasitic bipolar transistors is avoided.
To achieve this, a voltage multiplier circuit in accordance with the invention is characterized in that the field effect transistors of the elements on a substrate are realized in separate regions (e.
g.
wells) of a conductivity type other than that of the substrate, at least the rectifier elements which are situated at a high-voltage side of the circuit comprising respective switching means which connect internal diodes, formed in the field effect transistor by a p-n junctions between a source and a drain, respectively, of the field effect transistor on the one side and the region (e.
g.
well) on the other side, to either the source in the conductive state or to the drain in the blocked state of the field effect transistor, so that the internal diodes remain blocked.
When the region is connected to the source of the field effect transistor in the conductive state of the latter, the back-gate bias voltage remains zero.
When the region is connected to the drain of the field effect transistor in the blocked state of the latter, the parasitic bipolar transistor whose collector, base and emitter are formed by the substrate, the well and the drain, respectively, will not become conductive.
EMBODIMENTS OF THE INVENTION An embodiment of a voltage multiplier circuit in accordance with the invention is characterized in that the switching means of the first field effect transistor comprise a second and a third field effect transistor which are of the same conductivity type as the first field effect transistor and which are realized in respective regions which are coupled to the region of the first field effect transistor, a source of the second and the third field effect transistor being connected to a source and a drain, respectively, of the first field effect transistor, a control electrode of the second and the third field effect transistor being coupled to the drain and the source, respectively, of the first field effect transistor, the drains of the second and the third transistor being connected to the interconnected regions
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