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Hexagonal mesh multiprocessor system
| Details |
Inventors: Shin, Kang G.; Chen, Ming-Syan; Kandlur, Dilip D.;
Assignee: The University of Michigan (Ann Arbor, MI)
Primary Examiner: Heckler; Thomas M.
Assistant Examiner:
Attorney, Agent or Firm: Rohm & Monsanto
An interconnection network for a plurality of process nodes, each illustratively comprised of a processor-memory pair, utilizes an hexagonal mesh arrangement of size n which is wrapped in each of the x, y, and z directions. In accordance with the invention, a unique address value is assigned to each processor node in the network, beginning at a central processor node and continuing along the x direction, and via the wrapping links, until each such processor node has a unique sequential address. Each of the rows, having first and last processor nodes therein, is wrapped by coupling each of the last processor nodes in each row to a respective first processor node in a corresponding row which is n-1 rows away. Point-to-point communication is achieved using the unique addresses of only the source and destination processor nodes, without requiring each intermediate processor node to contain global information about the entire network. An algorithm computes the shortest path between the source and destination processor nodes, in terms of the minimum number of processors which must be encountered by the message as it proceeds along the x, y, and z directions of the network toward the destination processor node. Each intermediate processor node updates the routing information. Point-to-point communication is also used to effect a broadcasting of a message from a source processor node to every other processor node in the network. |
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DETAILED DESCRIPTION FIG.
1 is a schematic representation of a regular, nonhomogenous interconnection graph 10 which is formed of a plurality of processor nodes 11 coupled to one another.
An interconnection graph is said to be "regular" if all of the processor nodes in the graph have the same degree, and "homogenous" if all of the nodes are topologically identical.
Although homogeneity implies regularity, the converse does not always hold true.
For example, interconnection graph 10 is regular, but not homogenous since node x and node y are not topologically identical.
FIG.
2 is a schematic representation of an hexagonal mesh arrangement 20 formed of a plurality of processor nodes 21 which are interconnected with each other.
All of processor nodes 21, except those disposed on the periphery of hexagonal mesh arrangement 20 are of degree six.
Hexagonal mesh 20 is of size 3 (n=3) since three processor nodes are present on each outer edge thereof.
FIG.
3 is a schematic representation of an hexagonal mesh arrangement 30 which has been partitioned into a plurality of rows in the x, y, and z directions.
Hexagonal mesh 30 is formed of a plurality of processor nodes 31 which are not shown in this figure, for sake of simplicity of the representation, to be connected to one another.
In addition, hexagonal mesh 30 has a central processor node 32 which has six oriented directions, each of which leads to one of its six nearest neighbors.
Any of the six directions can be defined as the x direction, the direction 60.
degree.
clockwise to the x direction as the y direction, and the direction 60.
degree.
clockwise to the y direction, as the z direction.
Once the x, y, and z directions are defined, any hexagonal mesh arrangement of size n can be partitioned into 2n-1 rows with respect to any of the three directions.
In this specific illustrative embodiment where n=3, the hexagonal mesh arrangement can be partitioned into five rows (0 to 4) in any of the three directions.
FIG.
3 illustrates schematically the rows in hexagonal mesh arrangement 30 partitioned with respect to the x, y, and z directions, respectively
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