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Image data transfer architecture and method for an electronic reprographic machine
| Details |
Inventors: Wegeng, Donald L.; Carter, Jeff C.; Ward, Joseph W.; Beaman, Thomas G.; Sosinski, Gregory C.; Austin, Todd M.;
Assignee: Xerox Corporation (Stamford, CT)
Primary Examiner: Coles, Sr.; Edward L.
Assistant Examiner: Vu; Kim Yen
Attorney, Agent or Firm: Oliff & Berridge
An image data transfer architecture in which control data and image data are isolated is provided. Bidirectional buffers isolate data buses from the control bus, thereby allowing control to be maintained by an 8-bit programmed microprocessor. The controller microprocessor does not handle image data thereby reducing complex software and support components required of prior multiple 16- and 32-bit microprocessor controller systems. Isolation is achieved by having multiple data buses handling image data at various stages of processing, such as, for example, input image data, compressed image data and output image data. Additional efficiencies are realized by eliminating the inherent delays caused when high speed image output terminals are forced to share data buses with much lower speed image input terminals. |
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DETAILED DESCRIPTION If the image data and control signals are isolated from one another, the need for a complex common bus architecture with its associated high-end microprocessors, related support components and complex software would be eliminated.
Further, in view of the above problems relating to highly complex ESS architectures in high speed ER machines, what is needed is a simplified ESS architecture that efficiently controls the flow of image data from the IIT to the IOT and isolates the image data from the control signals, without degrading system performance.
Specifically, an architecture utilizing an 8-bit general purpose microprocessor to control data flows over a number of task-specific data buses that are isolated from one another and from the control signals on a separate control bus is needed.
In order to overcome the above and other problems and deficiencies with respect to electronic reprographic systems, the present invention provides an ESS architecture utilizing an isolated multiple bus architecture using a simple 8-bit microprocessor to control data transfers from the IIT to the IOT.
It is, therefore, an object of the present invention to provide an electronic reprographic system having a high speed ESS architecture utilizing a simple programmed 8-bit microprocessor as a controller.
It is another object of the present invention to provide an architecture in which control data is isolated from image data.
It is another object of the present invention to provide a system that uses inherent time constraints of the image input terminal and the image output terminal to realize efficiencies heretofore unrecognized.
It is another object of the present invention to use a multiple bus architecture to isolate various data transfers within the system, thereby providing less complex yet highly efficient data transfers.
It is yet another object of the present invention to reduce the cost and complexity of existing electronic reprographic systems by providing a high speed electronic subsystem using a programmed 8-bit microprocessor for handling control signals only in place of multiple 16- and 32-bit microprocessors that handle both image data and control signals
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