Optimized FIFO memory

DETAILED DESCRIPTION The foregoing and other needs are substantially met through provision of a method and a system for optimizing graphics commands processing in a graphics processor.
The present invention enables the graphics processor to efficiently use the graphics processor's internal memory storage for both graphics commands and data when the supplied data is necessary for executing the graphics command.
Primitive parameter values are generated by software in a host processor and are provided to the graphics processor in the form of a display list.
The display list generally includes operational code instructions (opcode) which indicate the type of command to be performed and the corresponding display data.
In a preferred embodiment, the graphics processor includes a bus-mastering interface unit for fetching the display list either directly from the host processor or from system memory through a read operation.
The bus-mastering interface unit allows the graphics processor to operate in a processor mode by assuming control of the system bus in the computer system in order to process the fetched graphics commands and data without any interruption from any other system resources in the computer system.
Through a bus-mastering interface unit, the graphics processor is able to fetch the display list directly from system memory to decode graphics commands and any associated data to determine where or how to internally store the commands and data.
A preferred embodiment also includes an internal memory storage unit in the graphics processor.
The internal memory unit comprises a plurality of "First-In-First-Out" or "FIFO" registers for storing the fetched commands.
Data fetched with the commands by the bus-master interface unit is decoded and stored in the FIFO registers.
The FIFO registers are also used to buffer write operations in the graphics processor to a datapath unit in the graphics processor while the graphics processor is fetching or processing pre-fetched data.
The described embodiment provides the advantageous functionality of a graphics processor capable of internally grouping register writes into a sequential write operation to perform a continous write to a register file with a given display list instructions without having to register skip