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Expert system for identifying likely failure points in a digital data processing system |
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Technique for diagnosing and locating physical and logical faults in data transmission systems |
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Processor device for terminating and creating synchronous transport signals |
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Method and apparatus for shadow generation through depth mapping |
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Computer graphics system having per pixel fog blending |
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System for storage and retrieval of JPEG images |
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Programmable sequence controller
| Details |
Inventors: Suzuki, Isao; Yomogida, Toshihiko; Yokota, Tsuyoshi;
Assignee: Toyoda-Koki Kabushiki-Kaisha (Aichi, JP)
Primary Examiner: Springborn; Harvey E.
Assistant Examiner:
Attorney, Agent or Firm: Oblon, Fisher, Spivak, McClelland & Maier
A programmable sequence controller wherein in accordance with a sequence program read out from a memory, a logic operation circuit tests a logical value supplied from an input converter connected to an external input element and generates an output command signal based upon the result of the test. The output command signal is stored in an output memory which has two storage addresses for each external output element, each storage address corresponding to a particular memory storage element addressed by the sequence program. A gate circuit is connected to these two memory storage elements and inhibits the application of an output command signal from one of the memory storage elements to an output converter when the gate circuit receives a logical value from the input converter. When receiving an output command signal from the other of the two memory storage elements the gate circuit then applies this signal to the output converter. Thus, an output element connected to the output converter is energized immediately in response to the operation of an input element. |
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DETAILED DESCRIPTION Accordingly, it is a primary object of the present invention to provide an improved programmable sequence controller which is capable not only of inhibiting passage of an output command signal which energizes an external output element, in response to a signal from an external input element, but also of enabling passage of the output command signal in accordance with a stored sequence program. Another object of the invention is to provide a sequence controller of the character set forth above wherein a gate circuit on an input/output hybrid card is responsive to two output command signals for energizing an external output element. A further object of the invention is to provide a sequence controller of the character set forth above, which in addition to an input/output hybrid card connectable to both of external input and output elements, is also provided with an input card connectable only to external input elements and an output card connectable only to external output elements. Briefly, according to the present invention, there is provided a programmable sequence controller comprising a program memory, which is controlled by a read-out control circuit for successively reading out control instructions each of which includes a test command or an output command and associated address data. The sequence controller includes a data selector which applies the operational state of an external input element from an input converter to a logic operation circuit when the input element is designated by the address data. The logic operation circuit is responsive to the test command so as to test the operational state of the designated input element and is also responsive to the output command so as to send an output command signal to an addressable output memory based upon the result of the test. In the present invention, the output memory has at least two storage addresses for one external output element, each of which stores thereat the output command signal when designated by the address data accompanied by the output command
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