Second difference function generator

DETAILED DESCRIPTION The above objections of the prior art as well as others may be overcome by providing the combination of means for storing second or higher order differences of a function and means for providing values of that function from those differences.
The function may be trigonometric and may be sine, cosine or both.
First difference values are produced from the second difference values and the function values are produced from the first difference values.
Accumulators may be provided for performing these two functions.
In a preferred embodiment, difference values of a function are stored in data storage means which is addressed by sequential addressing means which preferably may be a counter.
The data storage means output is coupled to first adder means and first register means is coupled to the output of the first adder means.
Second adder means is coupled to the output of the first register means and second register means is coupled to outputs of the second adder means.
The data storage means is preferably a read-only memory with second difference values stored therein.
Outputs of the first register means may be coupled to inputs of the first adder means and outputs of the second register means may be coupled to inputs of the second adder means.
The register means is preferably means for temporarily storing a binary number of two or more bits and may have flip-flop storage for each bit.
An azimuth converter constructed in accordance with the present invention includes means coupled to a radar antenna for producing azimuth change pulses at spaced intervals.
Means for producing a binary count in response to the azimuth change pulses is coupled to first and second memory means which each store portions of cosine and sine second difference values.
Inputs of first cosine and sine adder means are alternately coupled to the first and second memory means.
First cosine and sine register means are coupled to the respective cosine and sine adder means and second cosine and sine register means are coupled to the respective adder means