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Home Heat Accumulators High-frequency-ECL-voltage-controlled-ring-oscillator

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Details
Inventors: Davis, Craig M.; Rasmussen, Richard R.;
Assignee: National Semiconductor Corporation (Santa Clara, CA)
Primary Examiner: LaRoche; Eugene R.
Assistant Examiner: Pascal; Robert J.
Attorney, Agent or Firm: Limbach, Limbach & Sutton

An emitter-coupled logic (ECL) gate configuration is provided that allows variations in the bias current for controlling propagation delay. The emitter coupled logic circuitry includes a plurality of input transistors having commonly-coupled emitters. The collector of each input transistor is connected to receive a control voltage. A current source is connected between the commonly-coupled emitters and ground. Circuitry, preferably a variable resistance, is connected between the collectors of the input transistors and a supply voltage. A bias voltage controls the charging current provided to the collectors of the ECL input transistors.

DETAILED DESCRIPTION OF THE INVENTION As shown in FIG.
4, the present invention provides an ECL gate configuration 100 that allows the bias current applied to the gate 100 to be varied.
This permits the propagation delay of the gate 100 to be changed by way of an input control voltage.
Controlling the propagation delay in this manner allows the ECL gate 100 to be used in voltage controlled oscillator applications, as will be described in greater detail below.
With continuing reference to FIG.
4, the structure of the ECL gate 100 is similar to a standard ECL logic gate except that each of the conventional ECL gate collector load resistors is replaced by a PMOS device 102 in parallel with a Schottky diode 104.
This configuration makes it possible to vary the gate's effective logic switching currents and propagation delays because the gate bias of the PMOS devices 102 can be varied to mimic an adjustable load resistor.
A Schottky diode 102 is present to limit the low level logic swing.
The pull-down current source, comprising NPN devices 1X and 2X, for the gate 100 is controlled by an identically biased PMOS control transistor 106.
Device 2X has twice the current sourcing capability of device 1X.
Thus, the current of device 106 is scaled up to be twice that of the upper PMOS source, i.
e.
elements 102 and 104, so that, during transitions, the charging currents at the collectors of the input transistors 108, 110 are matched.
The collector of the common-emitter, differential pair NPN transistor, i.
e.
either device 108 or device 110, which is "off" is held at a logic "high" level by one of the PMOS devices 102 at a 1X current sourcing magnitude.
The collector of the differential pair NPN transistor (108, 110) which is "on" is held "low" at one Schottky diode voltage drop below VCC by the pull-down current source device 2X.
The 2X current for the "low" level collector comprises 1X sourced by the appropriate PMOS device 102 and 1X sourced by the corresponding Schottky diode 104.
During switching transients, the net positive charging current is 1X



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