Interruptable voltage-controlled oscillator and phase-locked loop using same

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference is now made in detail to the present preferred embodiments of the invention which illustrate the best mode presently contemplated by the inventor for practicing the invention, the preferred embodiments of which are illustrated in the accompanying drawings.
The inventions described herein are part of a single integrated circuit device identified as the Advanced Micro Devices, Inc.
, AM7991 Serial Interface Adaptor designed for use in a ten megabit-per-second packet-switched local area network system.
This device detects the presence of received data on a transceiver cable and transforms a received Manchester-encoded data signal into a data output signal and a clock output signal.
Precision pulse delays, which are locked to the frequency of a reference signal are utilized within this integrated circuit device.
GATED RING OSCILLATOR FIG.
1 shows a gated ring oscillator circuit comprised of three inverter stages.
A first inverter stage 12 and a second inverter stage 14 are cascaded to feed one input terminal of a NOR gate 16 which has its output terminal connected through a signal line 18 to the input of the inverter 12.
The other input terminal 19 of the NOR gate 16 is used to gate the ring oscillator circuit on and off.
Generally, gated ring oscillators of this type use n inverter stages where n is an odd integer.
When the gate input at terminal 19 is low, the oscillator 10 runs with a period of t.
sub.
p =t.
sub.
pLHA +t.
sub.
pHLB +t.
sub.
pLHC +t.
sub.
pHLA +t.
sub.
pLHB +t.
sub.
pHLC.
where t.
sub.
pLH is the transition time for a gate going from a logical low output state to a logical high output state and where t.
sub.
pHL is the transition time for a gate going from a high to a low output state.
For equal t.
sub.
pLH and t.
sub.
pHL, then t.
sub.
p =3t.
sub.
PLH +3t.
sub.
PHL.
When the gate input at terminal 19 is high, the output of the NOR gate 16 is forced low so that the output of inverter 14 gives low after a time delay of 2t.
sub.
pHL +t.
sub.
pLH, that is, after the minimum time required for a rising output signal at the output of NOR gate 16 to propagate around the ring