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| Semiconductor memory device with reduced inter-band tunnel current |
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| Methods for diagnosing malfunctions in a disk drive |
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| Gate array with bidirectional symmetry |
| The invention is an improvement in a CMOS gate array comprising a plurality of core cells. The core ... |
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| Multiprocessor systems having distributed shared resources and deadlock prevention |
| FIG. 1 shows in block diagram a multiprocessor system in accordance with the present invention. T... |
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12C bus expansion apparatus and method therefor
| Details |
Inventors: Goodwin, Joel Gerard; Hartman, Steven Paul; Isensee, Scott Harlan; Tuten, Wally;
Assignee: International Business Machines Corporation (Armonk, NY)
Primary Examiner: Ray; Gopal C.
Assistant Examiner:
Attorney, Agent or Firm: Newberger; Barry S. Winstead Sechrest & Minick P.C., Van Leeuwen; Leslie A.
An apparatus and method for expansion of an inter-IC (I.sup.2 C) is provided. An expansion processor resides on a primary I.sup.2 C bus. The expansion processor is coupled to a plurality of I.sup.2 C sub-buses each of which may host a plurality of I.sup.2 C devices. Data is transferred between the expansion processor and the plurality of I.sup.2 C devices via the corresponding sub-bus according to an I.sup.2 C protocol. Data transfer is in response to a request initiated by a bus master on the primary I.sup.2 C bus. The bus master communicates with a target device residing on one of the sub-buses by addressing the expansion processor. The bus master informs the expansion processor of the target device by sending the expansion processor a number of the sub-bus on which the target device resides, and an address of the target device. A data stream bound for the target device is directed to the expansion processor which the echos it to the target device. Likewise, a data stream bound from the target device to the bus master on the primary I.sup.2 C bus is transmitted to the expansion processor which the echos it to the bus master. |
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DETAILED DESCRIPTION The aforementioned needs are addressed by the present invention.
Accordingly, there is provided in a first form, an apparatus for inter-IC (I.
sup.
2 C) bus expansion.
The apparatus includes an expansion processor operable for communicating on an I.
sup.
2 C bus.
The expansion processor is coupled to a plurality of I.
sup.
2 C sub-buses, wherein each sub-bus of the plurality is operable for transferring data between the expansion processor and a plurality of I.
sup.
2 C compatible devices, according to an I.
sup.
2 C protocol, in response to signals on the I.
sup.
2 C bus.
There is also provided, in a second form, a data processing system.
The data processing system includes a central processing unit (CPU) operable for communicating on an inter-IC (I.
sup.
2 C) bus, the CPU being operable as an I.
sup.
2 C bus master.
An expansion processor is coupled to the I.
sup.
2 C bus, the expansion processor is also coupled to a plurality of I.
sup.
2 C sub-buses, wherein each sub-bus of the plurality is operable for transferring data between the expansion processor and a plurality of I.
sup.
2 C compatible devices, according to an I.
sup.
2 C protocol, in response to signals on the I.
sup.
2 C bus.
Additionally, there is provided, in a third form, a method for inter-IC (I.
sup.
2 C) bus expansion.
The method includes snooping a primary I.
sup.
2 C for a preselected bus address.
On receiving the preselected address, a read operation or a write operation on a sub-bus is selected in response to a data value in a portion of the address.
There is also provided, in a fourth form, a computer program product adaptable for storage on program storage media.
The program product includes programming for snooping a primary I.
sup.
2 C bus for a preselected bus address.
The program product also includes programming for, on receiving the bus address, selecting a read operation or a write operation in response to a data value in a portion of the address.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood
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