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 Adaptive digital filter

Details
Inventors: Adams, Peter F.; Cowan, Colin F. N.;
Assignee: British Telecommunications public limited company (GB3)
Primary Examiner: Olms; Douglas W.
Assistant Examiner: Scutch, III; Frank M.
Attorney, Agent or Firm: Nixon & Vanderhye

A digital filter comprises a plurality of delay stages 41 such as shift register stages through which an input x(t) is fed. Each of a plurality of individually addressable random access memories 42 is addressed by the output of one of the delay stages and the output from the RAMs 42 are combined. An error signal adapts the values stored within the RAMs. The filter may also be extended such that each RAM receives an address input from more than one delay stage.

DETAILED DESCRIPTION According to one aspect of the present invention there is provided a digital filter comprising a plurality of delay stages through which an input signal is fed successively; a plurality of individually addressable random access memories, each of which is addressable by the output of one of said delay stages; means for combining the outputs read from said random access memories; and means for providing an error signal for adapting the values stored within said random access memories.
Preferably the digital filter also includes a random access memory which receives the input signal directly without being delayed.
The digital filter may be modified to model a linear dispersion preceding the non-linearity.
In a preferred embodiment of such a filter each random access memory may be addressed by the output from more than one of said delay stages.
Preferably each memory receives the output from the same number of delay stages, and said stages supplying a memory are adjacent stages.
According to a second aspect of the present invention there is provided a transmitter/receiver unit including a digital filter according to said first aspect in which said filter forms an echo copy signal for cancelling noise at the receiver due to an output from the transmitter.
Preferably each random access memory of the digital filter in said unit is addressed by a plurality of adjacent delay stages.



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