Apparatus and method for decreasing the access time to non-cacheable address space in a computer system

DETAILED DESCRIPTION We claim: 1.
In a computer system having at least one CPU, a memory, at least one cache capable of containing only certain selected information coupled to the CPU, and a multi-port bus controller interposed between the CPU, the memory, and at least one bus coupled to at least one peripheral, wherein accesses by the CPU to at least one of the memory and the peripheral cannot be stored in the cache, the multi-port bus controller comprising: means for determining if information requested by the CPU cannot be contained in the cache; and means for immediately commencing a bus cycle to request the information without waiting for a negative cache response, the bus cycle commencing at least one clock cycle earlier than when an access by the CPU to a cacheable address generates a cache miss.
2.
The computer system of claim 1 wherein addresses of accesses by the CPU that cannot be contained in the cache are distinct from addresses of accesses by the CPU that can be contained in the cache.
3.
The computer system of claim 2 wherein the means for determining if information requested by the CPU cannot be contained in the cache comprises an address decoder.
4.
The computer system of claim 3 wherein the address decoder comprises a programmable logic circuit.
5.
In a computer system having a CPU, a memory, a cache capable of maintaining only certain selected information coupled to the CPU, and a multi-port bus controller interposed between the CPU, the memory, and a non-cacheable expansion bus, the multi-port bus controller comprising: a programmable logic circuit for determining if information requested by the CPU cannot be contained in the cache; and means for immediately commencing a bus cycle to request the information from the expansion bus without waiting for a negative cache response, the bus cycle commencing at least one clock cycle earlier than when an access by the CPU to a cacheable address generates a cache miss.
6.
The computer system of claim 5 wherein the programmable logic circuit decodes the address of the CPU and generates an output if the address corresponds to an access to the expansion bus