Apparatus and method for modifying signals from a CPU to a memory card

DETAILED DESCRIPTION A computer system and method of operation is provided wherein the memory controller of the system generates first and second address signals, typically RAS signals, and address bits for Y rows of addresses in memory; and wherein the memory of the system is configured with Y+1 rows of addresses operable by a single address signal, typically a single RAS signal.
The system includes logic, preferably on an ASIC chip that converts one of said RAS signals from the memory controller, together with at least one address signal generated by the CPU and propagated by the system memory controller, to the high order address bit for the memory rows, thus constituting Y+1 rows of address activated space, and generates a master RAS signal when either RAS generated by the memory controller goes active.
The logic also provides for a refresh operation of all memory location during a RAS only refresh (ROR) operation.