Apparatus for converting scan data of a keyboard

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The present invention will now be described more specifically with reference to the drawings attached only by way of example.
Throughout the specification, the same symbols and the equivalent part are described in the same reference numerals.
Referring to FIG.
2 for illustrating a scan data conversion circuit according to the present invention, a key matrix 12 has one key at each of the cross points where the rows cross the columns, and a given number of option switches, so as to produce the scan data SD when one of the keys is activated.
A scan decoder 14 decodes the scan data to produce a mode selecting data DD, a first scan data Ma, a second scan data Mb, and first and second clock signals LCKa and LCKb which are respectively synchronized with the first and second scan data Ma and Mb.
First and second latch circuits 16 and 18 latch the first and second scan data Ma and Mb according to first and second clock signals LCKa and LCKb.
A mode selection adder (option adder) 20 converts the first and second latched output data Ma' and Mb' first and second latch circuits 16 and 18 into the first and second scan conversion data Na' and Nb' according to the mode selecting data DD scan decoder The first and second data Ma and Mb are binary data of n bits, and the mode selecting data DD is the data to control the scan data conversion mode (hereinafter referred to as option data), having the bit states of OP.
sub.
1, OP.
sub.
2, OP.
sub.
3 and up/down (U/D.
sub.
A, U/D.
sub.
B).
Referring to FIG.
3, mode selection adder 20 includes an option state determining section including multiple inverters G.
sub.
1, G.
sub.
9, G.
sub.
10, AND gates G.
sub.
2, G.
sub.
3, G.
sub.
13 and OR gate G.
sub.
11, first data (Ma') conversion section including multiple AND gates G.
sub.
4, G.
sub.
6, G.
sub.
7, G.
sub.
8 and OR gate G.
sub.
5, and second data (Mb) conversion section including multiple AND gates G.
sub.
12, G.
sub.
14, G.
sub.
15 and OR gate G.
sub.
16.
Hereinafter the operation of the inventive structure will be described