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Apparatus for detecting intermittent and continuous faults in multiple conductor wiring and terminations for electronic systems
| Details |
Inventors: Sorensen, Brent A.;
Assignee:
Primary Examiner: Brown; Glenn W.
Assistant Examiner:
Attorney, Agent or Firm: Mallinckrodt & Mallinckrodt
A latching tester for testing continuity of wires in a system has an array of pin electronics cells, where each pin cell couples a signal to a row sense line and a column sense line when a change in current flow through a pin occurs; apparatus for detecting the signal on the row sense line; and apparatus for detecting the signal on the column sense line. The array of pin electronics cells may also operate as a capacitively coupled neural network, where a signal coupled onto the row and column lines from a stimulus line varies with the load on each pin of the pin electronics cells. An alternate mode of operation permits stimulus of the network and attached loads, and generation of a signature based upon the response of the network to the stimulus, as observed on the row and column sense lines. In yet another mode of operation, the tester may serve to recognize particular signals. |
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DETAILED DESCRIPTION The present invention comprises a neural network wherein the weighting factors of each synapse depend upon the characteristics of any external loading applied to a pin of each synapse.
The invention further comprises apparatus for stimulating the network, and for monitoring a response of the network to the stimulus.
The response of the network to the stimulus provides information about the loading applied to the pins that is useful in such applications as testing or analyzing a system of which the external loads form a part.
The network of the present invention operates as a tester capable of operating as a multichannel latching continuity tester.
The tester of the present invention comprises an array of pin interface circuits each comprising a couple of resistors and capacitors, together with row and column sense electronics including latches and comparators.
The array is so organized that if a pin interface circuit is attached to a wire of a wiring harness, and a change in continuity occurs on that wire, the faulty wire is identified to a microprocessor, which displays the discrepancies to a technician.
The tester of the present invention can also be operated in a static continuity test mode.
In this mode, each row of the array is probed to determine which pin interface circuits of that row are connected to a continuous circuit in the system being tested.
The resulting pattern of open and connected lines can be compared to a known good pattern, and any discrepancies identified by the microprocessor.
The tester may also be operated in a signature analysis mode, wherein a signature pattern is created that depends upon the pattern of diodes, resistances and capacitances in the system wiring under test.
Any significant variations between the signature pattern generated from the system, and a known good signature pattern in the microprocessor's memory, are then identified to the technician.
The microprocessor can also search its memory, using software neural network techniques, for signatures in its memory that most closely match the signature pattern generated from the system being tested
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I/O Systems 
