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Apparatus for programmable circuit and signal switching
| Details |
Inventors: Hsieh, Wen-Jai; Horng, Chi-Song; Wong, Chun C. D.;
Assignee: I-Cube, Inc. (Santa Clara, CA)
Primary Examiner: Hudspeth; David R.
Assistant Examiner:
Attorney, Agent or Firm: Smith-Hill and Bedell
A field programmable interconnect device (FPID) includes a set of ports and an array of switch cells for selectively interconnecting pairs of the ports. The switch cells are organized into a hierarchy of subarrays, and a control cell is provided for each subarray. Each switch cell includes a crosspoint switch and a single-bit memory. A bit stored in the memory indicates whether the switch, when enabled, is to interconnect its pair of FPID I/O ports. A data bit stored in each control cell indicates whether all switching cells of an associated subarray are enabled. In a "rapid connect" mode of operation, the FPID sets the state of the bit stored in any individual switch or control cell in response to parallel input data identifying the cell and indicating the state of the bit to be stored in the cell. In the rapid connect mode, the FPID can be programmed to rapidly switch connections between individual lines or between parallel buses connected to its ports. |
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DETAILED DESCRIPTION We claim: 1.
A programmable interconnect device for routing signals between signal ports in response to data from an external controller, the device comprising: switch means having a plurality of said signal ports, having memory means for storing a set of data bits, each data bit having a state indicating whether said switch means is to convey a signal between a separate pair of said signal ports associated with said data bit, and having means for conveying signals between each pair of signal ports when indicated by the state of the data bit associated with said pair of signal ports; and programming means for receiving said set of data bits in serial form from said external controller and storing the received set of data bits in said memory means, for receiving a multiple bit parallel data word from said external controller, said parallel data word identifying a particular bit of said set of data bits stored in said memory means and indicating a state to which said particular bit is to be set, and for setting said particular bit stored in said memory means to the indicated state.
2.
The programmable interconnect device in accordance with claim 1 wherein a portion of said signal ports are coupled to said external controller and to said programming means and wherein said programming means receives said parallel data word from said external controller via said portion of said signal ports.
3.
The programmable interconnect device in accordance with claim 1 wherein said switch means comprises a crosspoint switch array.
4.
The programmable interconnect device in accordance with claim 1 wherein said switch means comprises a folded crosspoint array comprising: a plurality of switch cells, each switch cell occupying a separate rectangle in a common plane of an integrated circuit, said rectangle having parallel first edges and adjacent second edges, said first edges being substantially longer than said second edges, each cell comprising a first conductor extending between said second edges of said rectangle, a second conductor extending between said second edges of said rectangle, a first memory cell for storing a separate one of said data bits, and means coupled to said first and second conductors and said first memory cell for selectively providing a signal path between said first and second conductors in response to a state of said separate one of said data bits
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I/O Systems 
