Arbitration circuitry for deciding access requests from a multiplicity of components

DETAILED DESCRIPTION We claim: 1.
In a data-handling system with a multiplicity n=2.
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m of components of different ranks served by a common data bus alternatively accessible by said components in an order of precedence based on their ranks, the combination therewith of a chain of n mutually identical arbitration devices respectively associated with and individually connected to said components, said arbitration devices being interlinked by a priority bus with m lines having a binary-tree structure including a first line connected to all n devices and an m.
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th line divided into n/2 sections each connected to a pair of adjacent devices, said devices following one another in a predetermined ranking order of the associated components, each of said arbitration devices comprising: register means for storing an m-bit priority code initially assigned to the respective device, the priority codes initially assigned to consecutive devices having numerical values varying progressively in conformity with said ranking order of the associated components; normally blocked gating means inserted between said priority bus and an output circuit of said register means for transmitting the stored priority code to said priority bus in the presence of an access request from the associated component; comparison means connected to said priority bus and to said output circuit for detecting an equality between the transmitted priority code and the state of energization of the lines of said priority bus in the presence of said access request, an arbitration device associated with a higher-ranking component modifying said state of energization by an overriding priority code simultaneously transmitted to the priority bus; and a control unit responsive to said access request for unblocking said gating means and sending a consent signal to the associated component in the presence of an equality determination by said comparison means, said consent signal enabling the associated component to access said data bus, each arbitration device further comprising calculating means having reference inputs connected to said priority bus inserted in series with a normally inactive driver in a loop between said output circuit and an input circuit of said register means for reloading same upon activation of said driver by a command from said control unit, said calculating means implementing the Boolean equation ##EQU1## where * stands for the AND function, XOR stands for the Exclusive-OR function, p