Architecture for data processor

DETAILED DESCRIPTION In carrying out the above and other objects of the invention in one form, there is provided a digital data processing system having an instruction decoder for decoding instructions and controlling operation of the data processing system.
An instruction register is coupled to the instruction decoder for storing instructions to be decoded.
A plurality of registers for storing data are arranged in an array and are coupled to a data bus.
The data bus is also coupled to an arithmetic and logic unit such that the data bus is suitable for transferring data from the array of registers to the arithmetic and logic unit.
The arithmetic and logic unit is used for performing operations on the data stored in the array of registers under the control of the instruction decoder.
A shift network for shifting the output of the arithmetic and logic unit is coupled between the arithmetic and logic unit and the data bus.
The data bus is also suitable for transferring the shift network output to the array of registers for storing the result.
An input/output means has a command shift register, at least one capture register, a timer register, a compare register, a control register, and a status register all coupled to the data bus.
The subject matter which is regarded as the invention is set forth in the appended claims.
The invention itself, however, together with further objects and advantages thereof, may be better understood by referring to the following detailed description taken in conjunction with the accompanying drawings.