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| Methods and apparatus for translating incompatible bus transactions |
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| Data-array processing system wherein parallel processors access to the memory system is optimized |
| OF THE PREFERRED EMBODIMENTS Preferred embodiments of the invention will now be described, by way ... |
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| Video signal memories |
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| Obtaining access to a two-dimensional portion of a digital picture signal |
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| Devices, systems and methods for accessing data using a pixel preferred data organization |
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| Display apparatus |
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Automatic pin circuitry shutoff for an integrated circuit
| Details |
Inventors: Wehrmacher, John R.;
Assignee: VLSI Technology, Inc. (San Jose, CA)
Primary Examiner: LaRoche; Eugene R.
Assistant Examiner: Dinh; Son
Attorney, Agent or Firm: Weller; Douglas L.
A method and circuitry allows for the prevention of tester induced failures and reliability problems which occur when a tester creates bus contention by overdriving output pins of an integrated circuit. For each input/output (I/O) pad which is used for the output of data, a first signal on an output data line is compared with a second signal which is currently on the I/O pad. When the output is enabled and the comparison indicates the first signal is not equal to the second signal, the I/O pad is isolated from the output data line. The I/O pad is isolated, and thus in shutdown mode, until the I/O pad is no longer being driven to a signal value which is different than the signal value of the first signal on the output data line. Further, each I/O pad may be electrically isolated from its output data line whenever a comparison for any I/O pad indicates that the signal for the I/O pad is not equal to the signal on its output data line. In one embodiment, once all of the I/O pads is in shutdown mode, they are held in shutdown mode until a reset signal is received. |
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DETAILED DESCRIPTION In accordance with the preferred embodiment of the present invention, a method and circuitry is provided which allow for the prevention of tester induced failures and reliability problems which occur when a tester creates bus contention by overdriving output pins of an integrated circuit.
For each input/output (I/O) pad which is used for the output of data, a first signal on an output data line is compared with a second signal currently on the I/O pad.
When the comparison indicates the first signal is not equal to the second signal and output is enabled, the I/O pad is isolated from the output data line.
The I/O pad is isolated, and thus in shutdown mode, until the I/O pad is no longer being driven to a signal value which is different than the value of the first signal on the output data line.
In order to provide for earlier detection of a tester causing bus contention and to provide for less toggling of individual I/O pads from shutdown to operation modes, each I/O pad may be electrically isolated from its output data line whenever a comparison for any I/O pad indicates output is enabled and the signal for the I/O pad is not equal to the signal on its output data line.
Also, in one embodiment, once any or all of the I/O pads is in shutdown mode, the I/O pads are held in shutdown mode until a reset signal is received.
The circuitry that implements the present invention may supplement the circuitry typically used with an I/O pad.
For example, typically an output data line is coupled to an I/O pad through a tri-state output buffer/amplifier.
The gate of the tri-state amplifier is typically controlled by an enable signal on an output enable line.
In the preferred embodiment of the present invention this signal on the gate of the tri-state amplifier is produced by a logical gate which performs a logical OR on the enable signal and a shutdown signal.
The shutdown signal is produced as follows.
For each I/O pad a logical Exclusive OR (XOR) is performed comparing the signal on the I/O pad with the signal on the output data line
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I/O Systems 
