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Details
Inventors: Likens, Thomas H.; Norcross, Thomas M.;
Assignee: National Semiconductor Corporation (Santa Clara, CA)
Primary Examiner: Cain; David C.
Assistant Examiner:
Attorney, Agent or Firm: Limbach & Limbach L.L.P.

An internal state machine controller in an integrated circuit containing a cryptographic implementation independently tests and verifies each of the encryption and decryption algorithms and modes within the implementation with minimal processor intervention. The cryptographic implementation automatically generates all input data and exercises all feedback modes independent of the core processor. Eliminating external test vectors results in a device less expensive to manufacture and verify. Since the cryptographic implementation tests are performed independent of the processor, other parts of the integrated circuit may be tested simultaneously with the testing of the cryptographic implementation. The processor loads in a single set of predetermined test vectors and then signals the state machine to start the testing of all the algorithms contained in the module. The output of each algorithm is used as the input of the next algorithm. The encrypted output from each algorithm is then fed back into the algorithms in reverse order and decrypted. At the end of this cycle the data returned should match the original data exactly. This is considered a cycle. The number of cycles is programmable depending on the test requirements and or fault coverage desired. In the preferred embodiment, the cryptographic implementation includes a cryptographic engine having encryption and decryption modes. Output Feedback (OFB), Electronic Codebook (ECB), Cipher Block Chaining (CBC), and Cipher Feedback (CFB) modes are supported in the preferred embodiment of the present invention.

DETAILED DESCRIPTION Previously, testing and verification were performed using costly external test vectors to obtain the desired test coverage.
Additional tests were also required for each of the commonly used feedback modes.
These common modes include (but are not limited to) Cipher-Block chaining (CBC), Output-Feedback (OFB), Cipher-Feedback (CFB), and Electronic-Codebook (ECB) modes.
The use of external test vectors increased the test time required to validate the device and added significantly to the overall expense of manufacturing the module.
Another major problem with the previous solution was that the testing of the module stalled testing of other modules contained in the since each module was verified serially.
Also prior solutions failed to address the serious problem of excessive time and RAM requirements for Power-On-Self-Test (POST) in the field.
The present invention employs an internal state-machine that independently tests and verifies each of the encryption algorithms contained within the device with minimal CPU intervention.
It automatically generates all input data and exercises all feedback modes independent of the core processor.
The method of testing according to the present invention is superior to that of related methods because no costly external test vectors are required.
Eliminating external test vectors results in a device less expensive to manufacture and verify.
Also since the tests are performed independent of the processor, it is possible to test other devices and modules in parallel with the encryption module.
This parallel effort reduces test time and overall manufacturing cost.
In addition it allows for higher fault coverage, an essential requirement when determining "known-good-die" at wafer sort.
This design employs a state machine controller that steps through each encryption mode automatically, eliminating the need for externally ROM stored test vectors.
The test algorithm takes advantage of the symmetric nature of modern encryption and decryption algorithms to simplify the engineer's task of final test verification



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