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Integratable, bus-oriented transmission system
It is an object of the invention to increase the switching speed given a data transmission system of the type initially defined and to avoid the disadvantages of a high ...
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Discharge circuit for a semiconductor memory including address transition detectors
Therefore, a main object of the present invention is to provide a semiconductor memory device which is capable of reliable and high speed reading and writing operation ...
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Readout circuit and method for multiphase memory array
Two multiplexers, one demultiplexer, and a state machine that controls the operation of the multiplexers and the demultiplexer are used to read data out of a multiphase ...
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Microcomputer with automatic refresh of on-chip dynamic RAM transparent to CPU
In accordance with one embodiment of the invention, a microcomputer device is disclosed containing a ROM for program memory, a read/write memory, and a CPU in a single ...
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Semiconductor memory device with variable self-refresh cycle
An object of the present invention is, therefore, to provide a semiconductor memory device in which power consumption in a self-refresh mode is reduced. Another object ...
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Memory device with programmable self-refreshing and testing methods therefore
We claim: 1. A programmable refresh circuit integrated with a semiconductor memory device having a memory array accessed through word lines and bit lines, said ...
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Variable propagation delay digital signal inverter
Briefly, in accordance with one embodiment of the invention, an electronically-controlled variable propagation delay digital signal inverter comprises a digital signal ...
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Synchronous semiconductor device with discontinued functions at power down
Accordingly, a general object of the present invention is to provide a novel and useful synchronous semiconductor device in which the disadvantages of the aforementioned ...
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Network monitoring system for cell delay variation
What is claimed is: 1. An apparatus for minimizing jitter caused during transmission of a data packet stream, comprising: a time stamp detector detecting time stamp ...
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Memory module arranged for data and parity bits
OF THE PREFERRED EMBODIMENT Dynamic random access memory arrays are generally described in U.S. Pat. No. 4,081,701, issued to White, et al. and assigned to Texas ...
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I/O Systems 
