BiCMOS bit line load for a memory with improved reliability

DETAILED DESCRIPTION Accordingly, there is provided, in one form, a bit line load coupled to a differential bit line pair in a block of the memory.
The bit line load comprises first, second, and third transistors, and a resistor.
The first transistor has a collector coupled to a power supply voltage terminal, a base for receiving a bias signal, and an emitter for providing a first reference voltage.
The resistor has a first terminal coupled to the power supply voltage terminal, and a second terminal coupled to the emitter of the first transistor.
The second transistor has a collector for receiving the first reference voltage, a base for receiving an equalization signal, and an emitter coupled to a bit line.
The third transistor has a collector for receiving the first reference voltage, a base for receiving the equalization signal, and an emitter coupled to a complementary bit line.
These and other objects, features and advantages will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.